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End pointer
Control data
14.5.4. Terminating Data Transfer in Master Mode
A procedure to terminate data transfer in master mode is shown below.
1. Wait for an end-of-transmission interrupt (SPIA_
2. Set the SPIA_nCTL.MODEN bit to 0 to disable the SPIA Ch.n operations.
3. Stop the 16-bit timer to disable the clock supply to SPIA Ch.n.
14.5.5. Data Transfer in Slave Mode
A data sending/receiving procedure and operations in slave mode are shown below. Figures
14.5.5.1 and 14.5.5.2 show a timing chart and flowcharts, respectively.
Data sending procedure
1. Check to see if the SPIA_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
2. Write transmit data to the SPIA_nTXD register.
3. Wait for a transmit buffer empty interrupt (SPIA_nINTF.TBEIF bit = 1).
4. Repeat Steps 2 and 3 until the end of transmit data.
Note:
Transmit data must be written to the SPIA_nTXD register after the SPIA_nINTF.TBEIF bit is set to 1 by
the time the sending SPIA_nTXD register data written is completed. If no transmit data is written
during this period, the data bits input from the SDIn pin are shifted and output from the SDOn pin
without being modified.
Data receiving procedure
1. Wait for a receive buffer full interrupt (SPIA_nINTF.RBFIF bit = 1).
2. Read the received data from the SPIA_nRXD register.
3. Repeat Steps 1 and 2 until the end of data reception.
Data transfer operations
The following shows the slave mode operations different from master mode:
Slave mode operates with the SPI clock supplied from the external SPI master to the SPICLKn
•
pin.The data transfer rate is determined by the SPICLKn frequency. It is not necessary to
control the 16-bit timer.
SPIA can operate as a slave device only when the slave select signal input from the external SPI
•
master to the #SPISSn pin is set to the active (low) level. If #SPISSn = high, the software
transfer control, the SPICLKn pin input, and the SDIn pin input are all ineffective.
If the #SPISSn signal goes high during data transfer, the transfer bit counter is cleared and data
•
in the shift register is discarded.
Slave mode starts data transfer when SPICLKn is input from the external SPI master after the
•
#SPISSn signal is asserted. Writing transmit data is not a trigger to start data transfer.
Therefore, it is not necessary to write dummy data to the transmit data buffer when
performing data reception only.
Data transmission/reception can be performed even in SLEEP mode, it makes it possible to
•
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Transfer source
SPIA_nRXD register address
Transfer destination
Memory address to which the last received data is stored
dst_inc
0x1 (+2)
dst_size
0x1 (haflword)
src_inc
0x3 (no increment)
src_size
0x1 (halfword)
R_power
0x0 (arbitrated for every transfer)
n_minus_1
Number of transfer data
cycle_ctrl
0x1 (basic transfer)
Seiko Epson Corporation
INTF.TENDIF bit = 1).
n
14-11
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