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RTCA Control Register (High Byte)
Register name
Bit
RTCACTLH
7
6–0
Bit 7
RTCTRMBSY
This bit indicates whether the theoretical regulation is currently executed or not.
1 (R): Theoretical regulation is executing.
0 (R): Theoretical regulation has finished (or not executed).
This bit goes 1 when a value is written to the RTCACTLH.RTCTRM[6:0] bits. The theoretical
regulation takes up to 1 second for execution. This bit reverts to 0 automatically after the
theoretical regulation has finished execution.
Bits 6–0
RTCTRM[6:0]
Write the correction value for adjusting the 1 Hz frequency to these bits to execute
theoretical regulation. For a calculation method of correction value, refer to "Theoretical
Regulation Function."
Notes:
•
When the RTCACTLH.RTCTRMBSY bit = 1, the RTCACTLH.RTCTRM[6:0] bits
cannot be rewritten.
•
Writing 0x00 to the RTCACTLH.RTCTRM[6:0] bits sets the RTCACTLH.RTCTRMBSY
bit to 1 as well. However, no correcting operation is performed.
RTCA Second Alarm Register
Register name
Bit
RTCAALM1
15
14–12
11–8
7–0
Bit 15
Reserved
Bits 14–12
RTCSHA[2:0]
Bits 11–8
RTCSLA[3:0]
The RTCAALM1.RTCSHA[2:0] bits and the RTCAALM1.RTCSLA[3:0] bits set the 10-second
digit and 1-second digit of the alarm time, respectively. A value within 0 to 59 seconds can
be set in BCD code as shown in Table 10.6.1.
RTCAALM1.RTCSHA[2:0] bits RTCAALM1.RTCSLA[3:0] bits
0x0
0x0
· · ·
0x0
0x1
· · ·
0x5
Bits 7–0
Reserved
10-10
Bit name
Initial
RTCTRMBSY
0
RTCTRM[6:0]
0x00
Bit name
Initial
–
0
RTCSHA[2:0]
0x0
RTCSLA[3:0]
0x0
–
0x00
Table 10.6.1 Setting Examples in BCD Code
Setting value in BCD code
Seiko Epson Corporation
Reset
R/W
H0
R
H0
W
Reset
R/W
–
R
H0
R/W
H0
R/W
–
R
Alarm (second) setting
0x0
0x1
· · ·
0x9
0x0
· · ·
0x9
Remarks
–
Read as 0x00.
Remarks
–
00 seconds
01 second
· · ·
09 seconds
10 seconds
· · ·
59 seconds
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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