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wake the CPU up using an SPIA interrupt.
Other operations are the same as master mode.
Notes:
If data of the number of bits specified by the SPIA_nMOD.CHLN[3:0] bits is received when
•
the SPIA_nINTF.RBFIF bit is set to 1, the SPIA_nRXD register is overwritten with the newly
received data and the previously received data is lost. In this case, the SPIA_nINTF.OEIF bit is
set.
When the clock for the first bit is input from the SPICLKn pin, SPIA starts sending the
•
datacurrently stored in the shift register even if the SPIA_nINTF.TBEIF bit is set to 1.
SPICLKn
#SPISSn
SDOn
SDIn
SPIA_nINTF.TBEIF
SPIA_nINTF.RBFIF
Software operations
Figure 14.5.5.1 Example of Data Transfer Operations in Slave Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7)
Data transmission
Read the SPIA_nINTF.TBEIF bit
SPIA_nINTF.TBEIF = 1 ?
Yes
Write transmit data to
the SPIA_nTXD register
Transmit data remained?
No
End
14.5.6. Terminating Data Transfer in Slave Mode
A procedure to terminate data transfer in slave mode is shown below.
1. Wait for an end-of-transmission interrupt (SPIA_nINTF.TENDIF bit = 1). Or determine end of transfer
via the received data.
2. Set the SPIA_nCTL.MODEN bit to 0 to disable the SPIA Ch.n operations.
14-12
1 2 3
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Data (W) → SPIA_nTXD
Data (W) → SPIA_nTXD Data (W) → SPIA_nTXD
No
Yes
Wait for an interrupt request
(SPIA_nINTF.TBEIF = 1)
Figure 14.5.5.2 Data Transfer Flowcharts in Slave Mode
Seiko Epson Corporation
1 2 3 4 5 6 7 8
SPIA_nRXD → Data (R) SPIA_nRXD → Data (R)
Data reception
Wait for an interrupt request
(SPIA_nINTF.RBFIF = 1)
Read receive data from
the SPIA_nRXD register
Receive data remained?
No
End
S1C31D50 TECHNICAL MANUAL
Yes
(Rev. 1.00)
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