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2.6. Control Registers
PWGA Control Register
Register name
Bit
PWGACTL
15–8
7–6
5
4
3–2
1–0
Bits 15–6
Reserved
Bit 5
REGDIS
This bit enables the VD1 regulator discharge function.
1 (R/WP):
0 (R/WP):
Bit 4
REGSEL
This bit controls the V
1 (R/WP):
0 (R/WP):
Bits 3–2
Reserved
Bits 1–0
REGMODE[1:0]
These bits control the V
PWGACTL.REGMODE[1:0] bits
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0x00
–
0x0
REGDIS
0
REGSEL
1
–
0x0
REGMODE[1:0]
0x0
Enable
Disable
regulator voltage mode.
D1
mode0
mode1
regulator operating mode.
D1
Table 2.6.1 Internal Regulator Operating Mode
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Reset
R/W
–
R
–
R
H0
R/WP
H0
R/WP
–
R
H0
R/WP
Operating mode
Economy mode
Normal mode
Reserved
Automatic mode
Remarks
–
2-21
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