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1.2. Block Diagram
CPU core, Interrupt
SWCLK
controller, and debugger
SWD
System clock
IOSC
oscillator
OSC1
OSC1
OSC2
oscillator
Clock
FOUT
generator
(CLG)
OSC3
OSC3
oscillator
OSC4
EXOSC
EXOSC
oscillator
System reset
controller
(SRC)
#RESET
Power-on
reset/
Brown-out
reset
(POR/BOR)
V
Power generator
DD
V
(PWGA)
SS
1-4
(Cortex-M0+)
Flash memory
V
pp
16-bit peripheral bus
DMA request
Interrupt signal
I/O port01
(PPORT)
I/O port23
(PPORT)
I/O
portOthers
(PPORT)
Watchdog
timer
(WDT2)
Real-time
clock
(RTCA)
Supply
voltage
detector
(SVD3) 1 Ch.
16-bit timer
(T16) 8Ch.
IR remote
controller
(REMC3)
1Ch.
Figure 1.2.1 S1C31D50 Block Diagram
Seiko Epson Corporation
Cache
controller
Cache RAM
512 bytes
192K bytes
DMA
controller
4 Ch.
P00-07
P10-17
P20-27
P30-37
P40-47
P50-57
P60-67
P70-77
P80-87
P90-95
PA0-A6
PD0-D5
RTC1S
EXSVD0-1
REMO
CLPLS
RAM
MTB
8K bytes
HW Processor
RAM
14K bytes
Quad
VDDQSPI
synchronous
QSDIO00-03
serial
QSPICLK0
interface
#QSPISS0
(QSPI) 1 Ch.
SDI0-2
Synchronous
SDO0-2
serial
SPICLK0-2
interface
#SPISS0-2
(SPIA) 3 Ch.
I2C
SDA0-2
SCL0-2
(I2C) 3 Ch.
USIN0-2
UART
USOUT0-2
(UART3) 3 Ch.
TOUT00-03
TOUT10-13
16-bit PWM
CAP00-03
timer
CAP10-13
EXCL00-01
(T16B) 2 Ch.
EXCL10-11
RFIN0
REF0
R/F converter
SENA0
(RFC) 1 Ch.
SENB0
RFCLKO0
12bit A/D
#ADTRG
convertor
ADIN00-07
(ADC12A) 1
VREFA0
Ch.
Sound_DAC
SDACOUT_P
SDACOUT_N
1 Ch.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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