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15.3.3. QSPI Clock (QSPICLK n ) Phase and Polarity
The QSPICLKn phase and polarity can be configured separately using the QSPI_nMOD.CPHA bit and the
QSPI_ nMOD.CPOL bit, respectively. Figure 15.3.3.1 shows the clock waveform and data input/output
timing in each set- ting.
QSPI_nMOD register
CPOL bit
CPHA bit
1
1
1
0
0
1
0
0
x
x
(Master mode, output)
x
x
(Slave mode, output)
x
1
(Slave mode, output)
x
0
Figure 15.3.3.1 QSPI Clock Phase and Polarity (QSPI_nMOD.LSBFST bit = 0, QSPI_nMOD.CHLN[3:0] bits =
15.4. Data Format
The QSPI data length can be selected from 2 to 16 clocks by setting the QSPI_nMOD.CHLN[3:0] bits. The
input/ output permutation is configurable to MSB first or LSB first using the QSPI_nMOD.LSBFST bit.
Figures 15.4.1 to
15.4.3 show data format examples in different transfer modes (QSPI_nMOD.TMOD[1:0]) when the
QSPI_nMOD. CPOL bit = 0 and the QSPI_nMOD.CPHA bit = 0.
Cycle No.
QSPI_nMOD.
QSPICLKn
LSBFST bit
QSDIOn0
0
QSDIOn1
QSDIOn0
1
QSDIOn1
Figure 15.4.1 Data Format Selection for Single Transfer Mode Using the QSPI_nMOD.LSBFST Bit
(QSPI_nMOD.TMOD[1:0] bits = 0x0, QSPI_nMOD.CHLN[3:0] bits = 0x7, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0)
15-8
Cycle No.
1
QSPICLKn
QSPICLKn
QSPICLKn
QSPICLKn
(Input)
MSB
QSDIOn
MSB
QSDIOn
MSB
QSDIOn
MSB
QSDIOn
Writing data to the QSPI_nTXD register
0x7)
1
2
Dw7
Dw6
Dw5
Dr7
Dr6
Dr5
Dw0
Dw1
Dw2
Dr0
Dr1
Dr2
Writing Dw[7:0] to the QSPI_nTXD register
Seiko Epson Corporation
2
3
4
5
3
4
5
6
Dw4
Dw3
Dw2
Dr4
Dr3
Dr2
Dw3
Dw4
Dw5
Dr3
Dr4
Dr5
Loading Dr[7:0] to the QSPI_nRXD register
6
7
8
LSB
LSB
LSB
LSB
7
8
Dw1
Dw0
Dr1
Dr0
Dw6
Dw7
Dr6
Dr7
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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