Epson S1C31D50 Technical Instructions page 106

7.7.6. P5 Port Group
The P5 port group consists of seven ports P50–P56 and they support the GPIO and interrupt functions.
Register name Bit
PPORTP5DAT 15–8
(P5 Port Data 7–0
Register)
PPORTP5IOEN 15–8
(P5 Port Enable
7–0
Register)
PPORTP5RCTL 15–8
(P5 Port Pull-
7–0
up/down Control
Register)
PPORTP5INTF 15–8
(P5 Port Interrupt
7–0
Flag Register)
PPORTP5INTCTL 15–8
(P5 Port Interrupt
7–0
Control Register)
PPORTP5CHATEN 15–8
(P5 Port Chattering
7–0
Filter Enable
Register)
PPORTP5MODSEL 15–8
(P5 Port Mode 7–0
Select Register)
PPORTP5FNCSEL 15–14
(P5 Port Function 13–12
Select Register)
11–10
9–8
7–6
5–4
3–2
1–0
P5SELy = 0
Port
name
GPIO
Peripheral
P50 P50 SOUND_DAC SDACOUT_P
P51 P51
SOUND_DAC SDACOUT_N
P52 P52
P53 P53
P54 P54
P55 P55
P56 P56
P57 P57
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Table 7.7.6.1 Control Registers for P5 Port Group
Bit name Initial
P5OUT[7:0] 0x00
P5IN[7:0] 0x00
P5IEN[7:0] 0x00
P5OEN[7:0] 0x00
P5PDPU[7:0] 0x00
P5REN[7:0] 0x00
– 0x00
P5IF[7:0] 0x00
P5EDGE[7:0] 0x00
P5IE[7:0] 0x00
– 0x00
P5CHATEN[7:0] 0x00
– 0x00
P5SEL[7:0] 0x00
P57MUX[1:0]
P56MUX[1:0]
P55MUX[1:0]
P54MUX[1:0]
P53MUX[1:0]
P52MUX[1:0]
P51MUX[1:0]
P50MUX[1:0]
Table 7.7.6.2 P5 Port Group Function Assignment
P5yMUX = 0x0 P5yMUX = 0x1
(Function 0) (Function 1)
Pin Peripheral
–
–
– – –
– – –
– – –
– – –
– – –
– –
Seiko Epson Corporation
Reset R/W
H0 R/W
H0 R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
– R
H0 R/W
H0 R/W
H0 R/W
– R
H0 R/W
– R
H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
P5SELy = 1
P5yMUX = 0x2
(Function 2)
Pin Peripheral
– –
– –
– –
– –
– –
– –
– –
Remarks
–
–
–
–
Cleared by writing 1.
–
–
–
–
P5yMUX = 0x3
(Function 3)
Pin Peripheral Pin
– – –
– – –
– – –
– – –
– – –
– – –
– – –
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