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SVD3 Status and Interrupt Flag Register
Register name
Bit
SVD3INTF
15–9
8
7–1
0
Bits 15–9
Reserved
Bit 8
SVDDT
The power supply voltage detection results can be read out from this bit.
1 (R): Power supply voltage (VDD, EXSVDn) < SVD detection voltage VSVD
0 (R): Power supply voltage (VDD, EXSVDn) ≥ SVD detection voltage VSVD
Bits 7–1
Reserved
Bit 0
SVDIF
This bit indicates the low power supply voltage detection interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Note:
The SVD3 internal circuit is initialized if the interrupt flag is cleared while SVD3 is in
operation after 1 is written to the SVD3CTL.MODEN bit.
SVD3 Interrupt Enable Register
Register name
Bit
SVD3INTE
15–8
7–1
0
Bits 15–1 Reserved
Bit 0
SVDIE
This bit enables low power supply voltage detection interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Notes:
•
If the SVD3CTL.SVDRE[3:0] bits are set to 0xa, no low power supply voltage detection
interrupt will occur, as a reset is issued at the same timing as an interrupt.
•
To prevent generating unnecessary interrupts, the corresponding interrupt flag should be
cleared before enabling interrupts.
11-10
Bit name
Initial
–
0x00
SVDDT
x
–
0x00
SVDIF
0
Bit name
Initial
Reset
–
0x00
–
0x00
SVDIE
0
Seiko Epson Corporation
Reset
R/W
–
R
–
R
–
R
H1
R/W
Cleared by writing 1.
or EXSVD detection voltage VSVD_EXT
or EXSVD detection voltage VSVD_EXT
R/W
–
R
–
R
H0
R/W
Remarks
–
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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