Advertisement
16.4.6. Data Reception in Slave Mode
A data receiving procedure in slave mode and the I2C Ch.n operations are shown below. Figures 16.4.6.1
and 16.4.6.2 show an operation example and a flowchart, respectively.
Data receiving procedure
1. When receiving one-byte data, write 1 to the I2C_nCTL.TXNACK bit.
2. Wait for a START condition interrupt (I2C_nINTF.STARTIF bit = 1).
3. Check to see if the I2C_nINTF.TR bit = 0 (reception mode).
(Start a data sending procedure if I2C_nINTF.TR bit = 1.)
4. Clear the I2C_nINTF.STARTIF bit by writing 1.
5. Wait for a receive buffer full interrupt (I2C_nINTF.RBFIF bit = 1) generated when a one-byte
reception has completed or an end of transfer interrupt (I2C_nINTF.BYTEENDIF bit = 1).
Clear the I2C_nINTF.BYTEENDIF bit by writing 1 after the interrupt has occurred.
6. If the next receive data is the last one, write 1 to the I2C_nCTL.TXNACK bit to send a NACK after it
is received.
7. Read the received data from the I2C_nRXD register.
8. Repeat Steps 5 to 7 until the end of data reception.
9. Wait for a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1) or a START condition interrupt
(I2C_nINTF.STARTIF bit = 1).
Go to Step 10 when a STOP condition interrupt has occurred.
i.
Go to Step 3 when a START condition interrupt has occurred.
ii.
10. Clear the I2C_nINTF.STOPIF bit and then terminate data receiving operations.
Data receiving operations
START condition detection and slave address check
It is the same as the data transmission in slave mode.
However, the I2C_nINTF.TR bit is cleared to 0 and the I2C_nINTF.TBEIF bit is not set.
If the I2C_nMOD.GCEN bit is set to 1 (general call address response enabled), the I2C Ch.n starts
data receiving operations when the general call address is received.
Slave mode can be operated even in SLEEP mode, it makes it possible to wake the CPU up using
an interrupt when an address match is detected.
Receiving the first data byte
After the valid slave address has been received, the I2C Ch.n sends an ACK and pulls down SCL
to low until 1 is written to the I2C_nINTF.STARTIF bit. This puts the I
state and the external master into standby state. When 1 is written to the I2C_nINTF.STARTIF bit,
the I2C Ch.n releases SCL and receives data sent from the external master into the shift register.
After eight-bit data has been received, the I2C Ch.n sends an ACK and pulls down SCL to low.
The received data in the shift register is transferred to the receive data buffer and the
I2C_nINTF.RBFIF and I2C_nINTF.BYTEENDIF bits are both set to 1. After that, the received data can
be read out from the I2C_nRXD register.
Receiving subsequent data
When the received data is read out from the I2C_nRXD register after the I2C_nINTF.RBFIF bit has been
set to 1, the I2C Ch.n clears the I2C_nINTF.RBFIF bit to 0, releases SCL, and receives subsequent
data sent from the external master. After eight-bit data has been received, the I2C Ch.n sends an ACK
and pulls down SCL to low. The received data in the shift register is transferred to the receive data
buffer and the I2C_ nINTF.RBFIF and I2C_nINTF.BYTEENDIF bits are both set to 1.
To return a NACK after eight-bit data is received, such as when terminating data reception, write 1
to the I2C_nCTL.TXNACK bit before the data reception is completed. The I2C_nCTL.TXNACK bit is
automatically cleared to 0 after a NACK has been sent.
STOP/repeated START condition detection
It is the same as the data transmission in slave mode.
16-14
Seiko Epson Corporation
C bus into clock stretching
2
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Advertisement
