Epson S1C31D50 Technical Instructions page 236

Bits 11–8 DUMLN[3:0]
These bits set the dummy cycle length in a number of clocks when accessing the external
Flash memory in the memory mapped access mode.
QSPI_nMMACFG2.DUMLN[3:0] bits
15-42
Table 15.8.6 Dummy Cycle Length Settings
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Dummy cycle length
16 clocks
15 clocks
14 clocks
13 clocks
12 clocks
11 clocks
10 clocks
9 clocks
8 clocks
7 clocks
6 clocks
5 clocks
4 clocks
3 clocks
2 clocks
Setting prohibited
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)