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9.4. Control Registers
WDT2 Clock Control Register
Register name
Bit
WDT2CLK
15–9
8
7–6
5–4
3–2
1–0
Bits 15–9
Reserved
Bit 8
DBRUN
This bit sets whether the WDT2 operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bits 7–6
Reserved
Bits 5–4
CLKDIV[1:0]
These bits select the division ratio of the WDT2 operating clock (counter clock). The clock
frequency should be set to around 256 Hz.
Bits 3–2
Reserved
Bits 1–0
CLKSRC[1:0]
These bits select the clock source of WDT2.
WDT2CLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
9-4
Bit name
Initial
–
0x00
DBRUN
0
–
0x0
CLKDIV[1:0]
0x0
–
0x0
CLKSRC[1:0]
0x0
Table 9.4.1 Clock Source and Division Ratio Settings
WDT2CLK.CLKSRC[1:0] bits
0x0
IOSC
1/65,536
1/32,768
1/16,384
1/8,192
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/WP
–
R
H0
R/WP
–
R
H0
R/WP
0x1
0x2
OSC1
OSC3
1/128
1/65,536
1/32,768
1/16,384
1/8,192
Remarks
–
0x3
EXOSC
1/1
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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