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11.6. Control Registers
SVD3 Clock Control Register
Register name
Bit
SVD3CLK
15–9
8
7
6–4
3–2
1–0
Bits 15–9
Reserved
Bit 8
DBRUN
This bit sets whether the SVD3 operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bit 7
Reserved
Bits 6–4
CLKDIV[2:0]
These bits select the division ratio of the SVD3 operating clock.
Bits 3–2
Reserved
Bits 1–0
CLKSRC[1:0]
These bits select the clock source of SVD3.
SVD3CLK. CLKDIV[2:0] bits
0x7, 0x6
0x5
0x4
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note:
The clock frequency should be set to around 32 kHz.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0x00
DBRUN
1
–
0
CLKDIV[2:0]
0x0
–
0x0
CLKSRC[1:0]
0x0
Table 11.6.1 Clock Source and Division Ratio Settings
0x0
IOSC
Reserved
1/512
1/256
1/128
1/64
1/32
1/16
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/WP
–
R
H0
R/WP
–
R
H0
R/WP
SVD3CLK.CLKSRC[1:0] bits
0x1
0x2
OSC1
OSC3
1/1
Reserved
1/512
1/256
1/128
1/64
1/32
1/16
Remarks
–
0x3
EXOSC
1/1
11-7
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