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SDAC Clock Control Register
Register name
Bit
SDACCLK
15–9
8
7-6
5-4
3-2
1-0
Bits 15–9
Reserved
Bit 8
DBRUN
This bit sets whether the SDAC operating clock is supplied in DEBUG mode or not.
1 (R/W):
0 (R/W):
Bits 7–6
Reserved
Bits 5-4
CLKDIV[1:0]
These bits select the division ratio of the SDAC operating clock.
Bits 3–2
Reserved
Bits 1-0
CLKSRC[1:0]
These bits select the clock source of SDAC.
SDACCLK
CLKDIV[1:0]
21-38
Bit name
Initial
–
0x00
DBRUN
0x0
-
0x0
CLKDIV[1:0]
0x0
-
0x0
CLKSRC[1:0]
0x0
Clock supplied in DEBUG mode.
No clock supplied in DEBUG mode .
0x0
IOSC
0x3
reserved
0x2
reserved
0x1
reserved
0x0
1/1
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/W
-
R
H0
R/W
H0
R/W
SDACCLK CLKSRC[1:0]
0x1
0x2
reserved
OSC3
reserved
reserved
reserved
reserved
1/1
Remarks
–
0x3
EXOSC
reserved
reserved
reserved
1/1
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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