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RFC Ch.n Control Register
Register name
Bit
RFC_nCTL
15–9
8
7
6
5–4
3–1
0
Bits 15–9
Reserved
Bit 8
RFCLKMD
This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock.
1 (R/W): Divided-by-two clock output
0 (R/W): Oscillation clock output
For more information, refer to "CR Oscillation Frequency Monitoring Function."
Bit 7
CONEN
This bit disables the automatic CR oscillation stop function to enable continuous oscillation
function.
1 (R/W): Enable continuous oscillation
0 (R/W): Disable continuous oscillation
For more information, refer to "CR Oscillation Frequency Monitoring Function."
Bit 6
EVTEN
This bit enables external clock input mode (event counter mode).
1 (R/W): External clock input mode
0 (R/W): Normal mode
For more information, refer to "Operating Modes."
Note:
Do not input an external clock before the RFC_nCTL.EVTEN bit is set to 1. The RFINn pin is
pulled down to V
Bits 5–4
Reserved
Bits 3–1
Reserved
Bit 0
MODEN
This bit enables the RFC operations.
1 (R/W): Enable RFC operations (The operating clock is supplied.)
0 (R/W): Disable RFC operations (The operating clock is stopped.)
Note:
If the RFC_nCTL.MODEN bit is altered from 1 to 0 during R/F conversion, the counter value
being converted cannot be guaranteed. R/F conversion cannot be resumed.
20-10
Bit name
Initial
–
0x00
RFCLKMD
0
CONEN
0
EVTEN
0
SMODE[1:0]
0x0
–
0x0
MODEN
0
level when the port function is switched for the R/F converter.
SS
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
–
R
H0
R/W
Remarks
–
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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