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Epson S1C31D50 Technical Instructions page 367

Cmos 32-bit single chip microcontroller
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21.5.5. RAM Check R/W Start Command
"RAM Check R/W Start" command can be set under "mc_state_idle" state.
"RAM Check R/W Start" command starts RAM read/write check, the state is moved to "mc_state_ram_rw"
after the memory check start.
.
"RAM Check R/W" check Write/Read 0xAAAA, 0x5555, to RAM.
After finishing the memory check, HW Processor makes an interrupt on default and goes to
"mc_state_idle".
Please check PROCESSING bit field in STATUS register, it show OK or ERROR after check, if ERROR is
occurred, please check RESULT register, it shows first fail address.
When a state transition is occurred, HW Processor makes an interrupt on default, the interrupt can be
masked by
INTMASK on
Table 21.5.5.1 shows "RAM Check R/W Start" command flow.
Cortex Set HW Processor
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
"21.5.11. Memory Check Function Registers".
Wait STATE = "mc_state_idle"
Wait STATUS.READY = mc_status_ready
Set Memory Check COMMAND
-
COMMAND: "RAM Check RW Start "
-
MEMADDR
- MEMSIZE
in Memory Check Function Registers(See Table 21.5.11.1)
Set HWPCMDTRG.HWP0TRG
Wait HWPINTF.HWP0IF = 1
Check STATE = "mc_state_ram_rw", if necessary
Wait HWPINTF.HWP0IF = 1
Check STATE = "mc_state_idle"
Check PROCESSING bit field in STATUS register
Check RESULT register if error is occurred
Figure 21.5.5.1 "RAM Check R/W Start" Command Flow
Seiko Epson Corporation
HW Processor interrupts to cortex
HW Processor interrupts to cortex
21-29

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