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Epson S1C31D50 Technical Instructions page 382

Cmos 32-bit single chip microcontroller
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0x0020 00a0–0x0020 00a4
Address
Register name
WDT2CLK
0x0020
(WDT2 Clock
00a0
Control Register)
WDT2CTL
0x0020
(WDT2 Control
00a2
Register)
WDT2CMP
0x0020
(WDT2 Counter
00a4
Com- pare Match
Register)
0x0020 00c0–0x0020 00d2
Address
Register name
RTCACTLL
(RTCA Control
0x0020
Register (Low
00c0
Byte))
RTCAALM1
0x0020
(RTCA Second
00c2
Alarm Register)
RTCAALM2
0x0020
(RTCA
00c4
Hour/Minute
Alarm Register)
RTCASWCTL
0x0020
(RTCA Stopwatch
00c6
Control Register)
B-4
Watchdog Timer (WDT2)
Bit
Bit name
15–9
8
DBRUN
7–6
5–4
CLKDIV[1:0]
3–2
1–0
CLKSRC[1:0]
15–11
10–9
MOD[1:0]
8
STATNMI
7–5
4
WDTCNTRST
3–0
WDTRUN[3:0]
15–10
9–0
CMP[9:0]
Real-time Clock (RTCA)
Bit
Bit name
7
6
RTCBSY
5
RTCHLD
4
RTC24H
3
2
RTCADJ
1
RTCRST
0
RTCRUN
15
14–12
RTCSHA[2:0]
11–8
RTCSLA[3:0]
7–0
15
14
RTCAPA
13–12
RTCHHA[1:0]
11–8
RTCHLA[3:0]
7
6–4
RTCMIHA[2:0]
3–0
RTCMILA[3:0]
15–12
BCD10[3:0]
11–8
BCD100[3:0]
7–5
4
SWRST
3–1
0
SWRUN
Seiko Epson Corporation
Initial
Reset
R/W
0x00
R
0
H0
R/WP
0x0
R
0x0
H0
R/WP
0x0
R
0x0
H0
R/WP
0x00
R
0x0
H0
R/WP
0
H0
R
0x0
R
0
H0
WP
0xa
H0
R/WP
0x00
R
0x3ff
H0
R/WP
Initial
Reset
R/W
0
R
0
H0
R
0
H0
R/W
0
H0
R/W
0
R
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
R
0x0
H0
R/W
0x0
H0
R/W
0x00
R
0
R
0
H0
R/W
0x0
H0
R/W
0x0
H0
R/W
0
R
0x0
H0
R/W
0x0
H0
R/W
0x0
H0
R
0x0
H0
R
0x0
R
0
H0
W
0x0
R
0
H0
R/W
S1C31D50 TECHNICAL MANUAL
Remarks
Always read as 0.
Remarks
Cleared by setting the
RTCACTLL.RTCRST bit to
1.
Cleared by setting the
RTCACTLL.RTCRST bit to
1.
Read as 0.
(Rev. 1.00)

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