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15.5.5. Data Reception in Register Access Master Mode
A data receiving procedure and operations in register access master mode are shown below. Figures
15.5.5.1 and show a timing chart and flowcharts, respectively.
Data receiving procedure
1. Set the QSPI_nCTL.DIR bit to 1 when QSPI Ch.n is set to dual or quad transfer mode. (This setting
is not necessary in single transfer mode.)
2. Assert the slave select signal for the external slave device to be accessed by controlling the
QSPI_nCTL. MSTSSO bit or the general-purpose output port used for an extra slave select signal
output (if necessary).
3. Check to see if the QSPI_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
4. Write dummy data (or transmit data) to the QSPI_nTXD register.
5. Wait for a transmit buffer empty interrupt (QSPI_nINTF.TBEIF bit = 1).
6. Write dummy data (or transmit data) to the QSPI_nTXD register.
7. Wait for a receive buffer full interrupt (QSPI_nINTF.RBFIF bit = 1).
8. Read the received data from the QSPI_nRXD register.
9. Repeat Steps 6 to 8 until the end of data reception.
10. Negate the slave select signal that has been asserted in Step 2 by controlling the
QSPI_nCTL.MSTSSO bit or the general-purpose output port (if necessary).
Note:
To perform continuous data reception without stopping QSPICLKn, Steps 8 and 6 operations
must be completed within the QSPICLKn cycles equivalent to "Data bit length - 1" after Step 7.
Data receiving operations
In single transfer mode (QSPI_nMOD.TMOD[1:0] bits = 0), QSPI Ch.n operates similar to legacy SPI
devices. The data receiving operation starts simultaneously with a data sending operation when
transmit data (may be dummy data if data transmission is not required) is written to the QSPI_nTXD
register. Transmit data are output from the QSDIOn0 pin and receive data are input from the
QSDIOn1 pin.
In dual or quad transfer mode (QSPI_nMOD.TMOD[1:0] bits = 1 or 2), transmit data are not sent at
data reception. Writing dummy data to the QSPI_nTXD register triggers the QSPI Ch.n to start
supplying the data transfer clock from the QSPICLKn pin to the slave device.
The QSPICLKn pin outputs the number of clocks specified by the QSPI_nMOD.CHLN[3:0] bits.
The receive data bits input from the QSDIOn pins, according to the transfer mode specified by
the QSPI_nMOD. TMOD[1:0] bits, are shifted into the shift register in sync with these clocks.
When the last clock is output from the QSPICLKn pin and receive data bits are all shifted into the shift
register, the received data is transferred to the receive data buffer and the QSPI_nINTF.RBFIF bit is set
to 1. At the same time QSPI Ch.n issues a receive buffer full interrupt request if the QSPI_nINTE.RBFIE
bit = 1. After that, the received data in the receive data buffer can be read through the QSPI_nRXD
register.
Note:
If data of the number of the bits specified by the QSPI_nMOD.CHLN[3:0] bits and QSPI_nMOD.
TMOD[1:0] bits is received when the QSPI_nINTF.RBFIF bit is set to 1, the QSPI_nRXD register is
overwritten with the newly received data and the previously received data is lost. In this case, the
QSPI_nINTF.OEIF bit is set.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Seiko Epson Corporation
15-15
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