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SDAC Control Register
Register name
Bit
SDACCTL
15–1 –
0
Bits 15–1
Reserved
Bit 0
SDACEN
This bit enables the SDAC operations.
1 (R/W):
0 (R/W):
SDAC Mode Register
Register name
Bit
SDACMODE
15–9
8
7-1
0
Bits 15–9
Reserved
Bit 8
PWMOUTEN
This bit enables the PWM signal output.
1 (R/W):
0 (R/W):
Bits 7–1
Reserved
Bit 0
MODE
This bit always must be set to 0.
SDAC Data Register
Register name
Bit
SDACDAT
15–10
9-0
Bits 15–10
Reserved
Bits 9–0
DAT
These bits is stored the sound data.
*This register is used by the HW Processor. This register should not be written while the HW Processor is
enabled.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
0x00
SDACEN
0x0
Enable SDAC operations.
(The operating clock is supplied.)
Disable SDAC operations.
(The operating clock is stopped.)
Bit name
Initial
–
0x00
PWMOUTEN
0x0
–
0x0
MODE
0x0
Enable PWM signal output.
Disable PWM signal output.
Bit name
Initial
–
0x00
DAT
0x0
Seiko Epson Corporation
Reset
R/W
–
R
–
H0
R/W
Reset
R/W
–
R
H0
R/W
–
R
H0
R/W
Reset
R/W
–
R
H0
R/W
Remarks
Remarks
–
Remarks
–
21-39
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