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WDT2 Control Register
Register name
Bit
WDT2CTL
15–11
10–9
8
7–5
4
3–0
Bits 15–11
Reserved
Bits 10–9
MOD[1:0]
These bits set the WDT2 operating mode.
WDT2CTL.
MOD[1:0] bits
0x3
0x2
0x1
0x0
Bit 8
STATNMI
This bit indicates that a counter compare match and NMI have occurred.
1 (R): NMI (counter compare match) occurred
0 (R): NMI not occurred
When the NMI generation function of WDT2 is used, read this bit in the NMI handler
routine to con- firm that WDT2 was the source of the NMI.
The WDT2CTL.STATNMI bit set to 1 is cleared to 0 by writing 1 to the WDT2CTL.WDTCNTRST
bit.
Bits 7–5
Reserved
Bit 4
WDTCNTRST
This bit resets the 10-bit counter and the WDT2CTL.STATNMI bit.
1 (WP): Reset
0 (WP): Ignored
0 (R): Always 0 when being read
Bits 3–0
WDTRUN[3:0]
These bits control WDT2 to run and stop.
0xa (WP):
Values other than 0xa (WP): Run
0xa (R):
0x0 (R):
Always 0x0 is read if a value other than 0xa is written.
Since an NMI or reset may be generated immediately after running depending on the
counter value, WDT2 should also be reset concurrently when running WDT2.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
–
0x00
MOD[1:0]
0x0
STATNMI
0
–
0x0
WDTCNTRST
0
WDTRUN[3:0]
0xa
Table 9.4.2 Operating Mode Setting
Operating mode
Reserved
RESET after NMI mode
If the WDT2CTL.STATNMI bit is not cleared to 0 after an
NMI has occurred due to a counter compare match, WDT2
issues a reset when the next compare match occurs.
NMI mode
WDT2 issues an NMI when a counter compare match
occurs.
RESET mode
WDT2 issues a reset when a counter compare match occurs.
Stop
Idle
Running
Seiko Epson Corporation
Reset
R/W
–
R
H0
R/WP
H0
R
–
R
H0
WP
H0
R/WP
Description
–
Remarks
–
Always read as 0.
–
9-5
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