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15.8. Control Registers
QSPI Ch.n Mode Register
Register name
Bit
QSPI_nMOD
15–12
11–8
7–6
5
4
3
2
1
0
Bits 15–12
CHDL[3:0]
These bits set the number of clocks to drive the serial output data lines. This setting is
required to output the XIP confirmation bit to Micron Flash memories or to output the
mode byte to Spansion Flash memories.
These bits must be set to a value smaller than or equal to the QSPI_nMOD.CHLN[3:0] bit
setting.
Note:
When using the QSPI in slave mode, the QSPI_nMOD.CHDL[3:0] bits should be set to the
same value as the QSPI_nMOD.CHLN[3:0] bits.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
CHDL[3:0]
0x7
CHLN[3:0]
0x7
TMOD[1:0]
0x0
PUEN
NOCLKDIV
LSBFST
CPHA
CPOL
MST
Table 15.8.1 Data Line Drive Length Settings
QSPI_nMOD.CHDL[3:0] bits
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Reset
R/W
H0
R/W
H0
R/W
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
Data line drive length
16 clocks
15 clocks
14 clocks
13 clocks
12 clocks
11 clocks
10 clocks
9 clocks
8 clocks
7 clocks
6 clocks
5 clocks
4 clocks
3 clocks
2 clocks
1 clock
Remarks
–
15-33
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