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Normal operations
SDA
SCL
When SDA = LOW is detected
SDA
SCL
SDA
SCL
16.4.9. Error Detection
The I2C includes a hardware error detection function.
Furthermore, the I2C_nINTF.SDALOW and I2C_nINTF.SCLLOW bits are provided to allow software to
check whether the SDA and SCL lines are fixed at low. If unintended low level is detected on SDA or SCL,
a software recovery processing, such as I2C Ch.n software reset, can be performed.
The table below lists the hardware error detection conditions and the notification method.
No.
Error detecting period/timing
1 While the I2C Ch.n controls SDA to high for sending address,
data, or a NACK
2 <Master mode only> When 1 is written to the I2C_nCTL.TX-
START bit while the I2C_nINTF.BSY bit = 0
3 <Master mode only> When 1 is written to the I2C_nCTL.TX-
STOP bit while the I2C_nINTF.BSY bit = 0
4 <Master mode only> When 1 is written to the I2C_nCTL.
TXSTART bit while the I2C_nINTF.BSY bit = 0 (Refer to "Au-
tomatic Bus Clearing Operation.")
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
START
condition
SDA check
1
2
n
SDA check
(n ≤ 9)
Bus clearing operation
1
2
10
Figure 16.4.8.1 Automatic Bus Clearing Operation
Table 16.4.9.1 Hardware Error Detection Function
Seiko Epson Corporation
Slave address + R/W
START
condition
STARTIF = 1
STARTIF = 1
ERRIF = 1
I
2
C bus line monitored and
error condition
SDA = low
SCL = low
SCL = low
SDA
Automatic bus clearing
failure
Notification method
I2C_nINTF.ERRIF = 1
I2C_nINTF.ERRIF = 1
I2C_nCTL.TXSTART = 0
I2C_nINTF.STARTIF = 1
I2C_nINTF.ERRIF = 1
I2C_nCTL.TXSTOP = 0
I2C_nINTF.STOPIF = 1
I2C_nINTF.ERRIF = 1
I2C_nCTL.TXSTART = 0
I2C_nINTF.STARTIF = 1
16-17
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