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not exist are read-only bits and are always fixed at 0.
To prevent generating unnecessary interrupts, the corresponding interrupt flag should be
cleared before enabling interrupts.
T16B Ch.n Comparator/Capture m Control Register
Register name
Bit
T16B_nCCCTLm
15
14–12
11–10
9–8
7
6
5
4–2
1
0
Bit 15
SCS
This bit selects either synchronous capture mode or asynchronous capture mode.
1 (R/W): Synchronous capture mode
0 (R/W): Asynchronous capture mode
For more information, refer to "Comparator/Capture Block Operations - Synchronous
capture mode/ asynchronous capture mode." The T16B_nCCCTLm.SCS bit is control bit for
capture mode and is in- effective in comparator mode.
Bits 14–12
CBUFMD[2:0]
These bits select the timing to load the comparison value written in the T16B_nCCRm
register to the compare buffer. The T16B_nCCCTLm.CBUFMD[2:0] bits are control bits for
comparator mode and are ineffective in capture mode.
Table 17.7.3 Timings to Load Comparison Value to Compare Buffer
T16B_nCCCTLm.
Count mode
CBUFMD[2:0] bits
0x7–0x5
0x4
Up mode
Down mode
Up/down mode When the counter becomes equal to the comparison value set previously
0x3
Up mode
Down mode
Up/down mode When the counter becomes equal to the comparison value set previously
0x2
Up mode
Down mode
Up/down mode
0x1
Up mode
Down mode
Up/down mode When the counter reaches 0x0000 or the MAX value
0x0
Up mode
Down mode
Up/down mode
Bits 11–10
CAPIS[1:0]
These bits select the trigger signal for capturing (see Table 17.7.4). The
T16B_nCCCTLm.CAPIS[1:0] bits are control bits for capture mode and are ineffective in
comparator mode.
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Bit name
Initial
SCS
0
CBUFMD[2:0]
0x0
CAPIS[1:0]
0x0
CAPTRG[1:0]
0x0
–
0
TOUTMT
0
TOUTO
0
TOUTMD[2:0]
0x0
TOUTINV
0
CCMD
0
When the counter becomes equal to the comparison value set previously
Also the counter is reset to 0x0000 simultaneously.
When the counter becomes equal to the comparison value set previously
Also the counter is reset to the MAX value simultaneously.
Also the counter is reset to 0x0000 simultaneously.
When the counter reverts to 0x0000
When the counter reverts to the MAX value
or when the counter reverts to 0x0000
When the counter becomes equal to the comparison value set previously
When the counter reaches the MAX value
When the counter reaches 0x0000
At the CLK_T16Bn rising edge after writing to the T16B_nCCRm register
Seiko Epson Corporation
Reset
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
–
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
Comparison Value load timing
Reserved
Remarks
–
17-31
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