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4.2. Bus Access Cycle
The CPU uses the system clock for bus access operations. First, "Bus access cycle," "Device size," and
"Access size" are defined as follows:
•
Bus access cycle: One system clock period = 1 cycle
•
Device size:
cycle
•
Access size:
transfer)
Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral
circuits can be accessed with an 8- or 16-bit instruction.
4-2
Bit width of the memory and peripheral circuits that can be accessed in one
Access size designated by the CPU instructions (e.g., LDR Rt, [Rn] → 32-bit data
Table 4.2.1 Number of Bus Access Cycles
Device size
Access size
8 bits
8 bits
16 bits
32 bits
16 bits
8 bits
16 bits
32 bits
32 bits
8 bits
16 bits
32 bits
Seiko Epson Corporation
Number of bus access
cycles
1
2
4
1
1
2
1
1
1
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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