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15.5.3. Initialization
QSPI Ch.n should be initialized with the procedure shown below.
1. <Master mode only> Generate a clock by controlling the 16-bit timer and supply it to QSPI Ch.n.
2. Configure the following QSPI_nMOD register bits:
QSPI_nMOD.PUEN bit
-
QSPI_nMOD.NOCLKDIV bit
-
QSPI_nMOD.LSBFST bit
-
QSPI_nMOD.CPHA bit
-
QSPI_nMOD.CPOL bit
-
QSPI_nMOD.MST bit
-
3. Configure the following register bits when using memory mapped access mode:
QSPI_nMMACFG1.TCSH[3:0] bits
-
QSPI_nRMADRH.RMADR[31:20] bits
-
QSPI_nMMACFG2.DUMDL[3:0] bits
-
QSPI_nMMACFG2.DUMLN[3:0] bits
-
QSPI_nMMACFG2.DATTMOD[1:0] bits
-
QSPI_nMMACFG2.DUMTMOD[1:0] bits
-
QSPI_nMMACFG2.ADRTMOD[1:0] bits
-
QSPI_nMMACFG2.ADRCYC bit
-
QSPI_nMB.XIPACT[7:0] bits
-
QSPI_nMB.XIPEXT[7:0] bits
-
4. Assign the QSPI Ch.n input/output function to the ports. (Refer to the "I/O Ports" chapter.)
5. Set the following QSPI_nCTL register bits:
Set the QSPI_nCTL.SFTRST bit to 1.
-
Set the QSPI_nCTL.MODEN bit to 1.
-
6. Set the following bits when using the interrupt:
Write 1 to the interrupt flags in the QSPI_nINTF register.
-
Set the interrupt enable bits in the QSPI_nINTE register to 1. * (Enable interrupts)
-
*The initial value of the QSPI_nINTF.TBEIF bit is 1, therefore, an interrupt will occur immediately
after the QSPI_nINTE.TBEIE bit is set to 1.
7.
Configure the DMA controller and set the following QSPI control bits when using DMA transfer:
Write 1 to the DMA transfer request enable bits in the QSPI_nTBEDMAEN, QSPI_nRBFDMAEN, and
-
QSPI_nFRLDMAEN registers.
15-12
(Enable input pin pull-up/down)
(Select master mode operating clock)
(Select MSB first/LSB first)
(Select clock phase)
(Select clock polarity)
(Select master/slave mode)
(Set slave select signal negation period)
(Set remapping address)
(Select dummy cycle drive length)
(Select dummy cycle length)
(Select data cycle transfer mode)
(Select dummy cycle transfer mode)
(Select address cycle transfer mode)
(Select 24 or 32-bit address cycle)
(Set XIP activation mode byte)
(Set XIP termination mode byte)
(Execute software reset)
(Enable QSPI Ch.n operations)
(Enable DMA transfer requests)
Seiko Epson Corporation
(Clear interrupt flags)
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
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