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Epson S1C31D50 Technical Instructions page 237

Cmos 32-bit single chip microcontroller
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Bits 7–6
DATTMOD[1:0]
These bits select the transfer mode for the data cycle when accessing the external Flash
memory in the memory mapped access mode.
Table 15.8.7 Transfer Mode for Data, Dummy, and Address Cycles
QSPI_nMMACFG2.DATTMOD[1:0] bits
QSPI_nMMACFG2.DUMTMOD[1:0] bits
QSPI_nMMACFG2.ADRTMOD[1:0] bits
0x3
0x2
0x1
0x0
Bits 5–4
DUMTMOD[1:0]
These bits select the transfer mode for the dummy cycle when accessing the external Flash
memory in the memory mapped access mode.
Bits 3–2
ADRTMOD[1:0]
These bits select the transfer mode for the address cycle when accessing the external Flash
memory in the memory mapped access mode.
Bit 1
ADRCYC
This bit selects the address mode from 24 and 32 bits when accessing the external Flash
memory in the memory mapped access mode.
1 (R/W): 32-bit address mode (4-byte address cycle)
0 (R/W): 24-bit address mode (3-byte address cycle)
Bit 0
MMAEN
This bit enables memory mapped access mode for accessing the external Flash memory.
1 (R/W): Enable memory mapped access mode
0 (R/W): Disable memory mapped access mode (register access mode)
When this bit is altered from 1 to 0, the QSPI sends extra address and dummy cycles to
the external Flash memory. The address cycle outputs either a three or four-byte address
according to the QSPI_ nMMACFG2.ADRCYC bit setting, with all address bits set to 1. The
dummy cycle is output according to the QSPI_nMMACFG2.DUMLN[3:0] and
QSPI_nMMACFG2.DUMDL[3:0] bit settings, with a mode byte for terminating the XIP
session of the external Flash memory that has been configured using the
QSPI_nMB.XIPEXT[7:0] bits.
Note:
Slave mode does not support memory mapped access mode, therefore, setting the
QSPI_nMMACFG2.MMAEN bit to 1 does not take effect when the QSPI_nMOD.MST bit
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Transfer mode
Reserved
Quad transfer mode
The QSDIOn[3:0] pins are used.
Dual transfer mode
The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used.
Single transfer mode
The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used.
Seiko Epson Corporation
= 0.
15-43

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