Power-Fail Compare Mode - NEC V850ES/F 3-L Series User Manual

32-bit single-chip microcontroller
Table of Contents

Advertisement

Chapter 19

19.4.4 Power-fail compare mode

(1)
ANI1
A/D
conversion
ADA0CR1
INTAD
Conversion start
Set ADA0CE bit = 1
Figure 19-8
688
The A/D conversion end interrupt request signal (INTAD) can be controlled as
follows by the ADAnPFM and ADAnPFT registers.
• When the ADAnPFE bit = 0, the INTAD signal is generated each time
conversion is completed (normal use of the A/D Converter).
• When the ADAnPFE bit = 1 and when the ADAnPFC bit = 0, the value of the
ADAnCRmH register is compared with the value of the ADAnPFT register
when conversion is completed, and the INTAD signal is generated only if
ADAnCR0H ≥ ADAnPFT.
• When the ADAnPFE bit = 1 and when the ADAnPFC bit = 1, the value of the
ADAnCRmH register is compared with the value of the ADAnPFT register
when conversion is completed, and the INTAD signal is generated only if
ADAnCR0H < ADAnPFT.
In the power-fail compare mode, four modes are available as modes in which
to set the ANInm pins: continuous select mode and continuous scan mode,
one-shot select mode and one-shot scan mode.
Continuous select mode
In this mode, the result of converting the voltage of the analog input pin
specified by the ADAnS register is compared with the set value of the
ADAnPFT register. If the result of power-fail comparison matches the condition
set by the ADAnPFC bit, the conversion result is stored in the ADAnCRm
register, and the INTAD signal is generated. If it does not match, the
conversion result is stored in the ADAnCRm register, and the INTAD signal is
not generated. After completion of the first conversion, the next conversion is
started, unless the ADAnCE bit of the ADAnM0 register is cleared to 0.
Data1
Data2
Data 1
Data 2
(ANI1)
(ANI1)
Data 1
(ANI1)
ADA0PFT
ADA0PFT
unmatch
unmatch
Timing example of continuous select mode operation
(when power-fail comparison is made: ADA0S register = 01H)
User's Manual U18743EE1V2UM00
Data4
Data5
Data3
Data 3
Data 4
Data 5
(ANI1)
(ANI1)
(ANI1)
Data 2
Data 3
Data 4
(ANI1)
(ANI1)
(ANI1)
ADA0PFT
ADA0PFT
match
match
A/D Converter (ADC)
Data6
Data7
Data 6
Data 7
(ANI1)
(ANI1)
Data 6
(ANI1)
ADA0PFT
match
Conversion start
Set ADA0CE bit = 1

Advertisement

Table of Contents
loading

Table of Contents