Stand-By Control Registers - NEC V850ES/F 3-L Series User Manual

Clock Generator

4.2.3 Stand-by control registers

(1)
Access
Address
Initial Value
Table 4-14
Bit position Bit name
6 NMI1M
5 NMI0M
4 INTM
1 STP
Caution
These registers control and reflect the various stand-by modes that can be
entered for saving power.
PSC - Power save control register
The 8-bit PSC register controls the stand-by function. The STP bit of this
register specifies the stand-by mode.
This register can be read/written in 8-bit or 1-bit units.
Writing to this register is protected by a special sequence of instructions.
Please refer to "Write Protected Registers" on page 155 for details.
FFFF F1FE .
H
00 . The register is initialized by any reset.
H
7 6 5
0 NMI1M NMI0M
R R/W R/W
PSC register contents
Stand-by mode release control by occurrence of INTWDT2 signal:
0: Enable releasing stand-by mode by INTWDT2 signal.
1: Disable releasing stand-by mode by INTWDT2 signal.
Stand-by mode release control by NMI pin input:
0: Enable releasing stand-by mode by NMI pin input.
1: Disable releasing stand-by mode by NMI pin input.
Stand-by mode release control by maskable interrupt request signal:
0: Enable releasing stand-by mode by maskable interrupt request signal.
1: Disable releasing stand-by mode by maskable interrupt request signal.
Setting of stand-by mode:
0: Normal mode.
1: Stand-by mode.
Note: 1. Stand-by modes that can be set by the STP bit: IDLE1 mode, IDLE2
mode, STOP mode, and sub-IDLE mode.
2. Before setting this bit, set the bits PSMR.PSM[1:0].
When writing to this register, follow the instructions given in "CPU System
Functions" on page 135.
Entering a power save mode requires some attention, refer to "Power save
mode activation" on page 213.
Entering a power save mode requires special attention, refer to "Power save
mode activation" on page 213.
User's Manual U18743EE1V2UM00
4 3 2
INTM 0 0
R/W R R
Function
Chapter 4
1 0
STP 0
R/W R
181