Controlling The Pll; Watch Dog Timer Clock; Clkout Function - NEC V850ES/F 3-L Series User Manual

Clock Generator

4.4.6 Controlling the PLL

Using the PLL
Not using the PLL

4.4.7 Watch Dog Timer Clock

4.4.8 CLKOUT function

After the RESET signal has been released, the PLL has to be started by
PLLCTL.PLLON = 1, after the main oscillator has stabilized
(OSTC.MSTS = 1).
Since the default mode is the clock-through mode (PLLCTL.SELPLL = 0),
select the PLL mode (PLLCTL.SELPLL = 1).
• To operate the PLL from the stopped status, set PLLCTL.PLLON = 1, and
then set PLLCTL.SELPLL = 1 after the LOCKR.LOCK bit = 0 (the lockup
time can be counted by setting the lockup time to the PLLS register and
monitoring the LOCK flag of the LOCKR register).
• To stop the PLL, first select the clock-through mode (PLLCTL.SELPLL = 0),
wait for 8 clocks or more, and then stop the PLL (set PLLCTL.PLLON = 0).
When shifting to the IDLE2 or STOP mode while remaining in the PLL
operation mode, set the OSTS register as follows:
• STOP mode: Oscillation stabilization time > PLL lockup time
• IDLE2 mode: Setup time > PLL lockup time
When shifting to the IDLE1 mode, the PLL does not stop. Stop the PLL if
necessary.
The clock-through mode (PLLCTL.SELPLL = 0) is selected after the RESET
signal has been released. The PLL is stopped by default.
After reset release, the Watchdog Timer WDT2 is operating on the 240 KHz
internal oscillator (f /8 = 30 KHz approx.).
RL
When the MainOSC has stabilized, the Watchdog Timer can be clocked by the
MainOSC (f /128).
X
The clock output function is used to output the CPU system clock (f
the CLKOUT pin.
The status of the CLKOUT pin is the same as the CPU system clock. The pin
can output the clock when it is in the operable status. It outputs a low level in
the stopped status.
User's Manual U18743EE1V2UM00
Chapter 4
) from
VBCLK
215