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Chapter 4
(6)
Access
Address
Initial Value
Table 4-9
Bit position
Bit name
4
PCLE
1 to 0
PCK[1:0]
Note
176
PCLM - Programmable clock mode register
The 8-bit PCLM register specifies the setting the programmable clock output
PCL.
This register can be read/written in 1-bit or 8-bit units.
FFFF F82F
.
H
00
. The register is initialized by any reset.
H
7
6
5
0
0
0
R
R
R
PCLM register contents
PCL enable:
0: PCL disabled (PCL pin is fixed to low level).
1: PCL enabled.
PCL clock frequency selection:
PCK1
PCK0
0
0
0
1
1
0
1
1
A PCL clock is only output when the PLL is in locked status.
User's Manual U18743EE1V2UM00
4
3
2
PCLE
0
0
R/W
R
R
Function
PCL output clock
f
PCL
f
PCL
f
PCL
f
PCL
Clock Generator
1
0
PCK1
PCK0
R/W
R/W
= f
/4
PLLO
= f
/8
PLLO
= f
/16
PLLO
= f
/32
PLLO
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