Page 1 User’s Manual V850ES/Fx3-L 32-bit Single-Chip Microcontroller Hardware V850ES/FE3-L: V850ES/FF3-L: V850ES/FG3-L: µPD70F3610 µPD70F3615 µPD70F3620 µPD70F3611 µPD70F3616 µPD70F3621 µPD70F3612 µPD70F3617 µPD70F3622 µPD70F3613 µPD70F3618 µPD70F3614 µPD70F3619 Document No. U18743EE1V2UM00 Date Published June 2008 © NEC Electronics 2008 Printed in Germany...
Page 2 User’s Manual U18743EE1V2UM00...
Page 3 Notes for CMOS Devices 1. Precaution against ESD for semiconductors Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 4 “quality assurance program” for a specific application. The recommended applications of NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard":...
Page 5 The quality grade of NEC Electronics products is “Standard” unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact NEC Electronics sales representative in advance to determine NEC Electronics 's willingness to support a given application.
Page 6 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 7 Preface Readers This manual is intended for users who want to understand the functions of the concerned microcontrollers. Purpose This manual presents the hardware manual for the concerned microcontrollers. Organization This system specification describes the following sections: • Pin function •...
Page 8 Preliminary versions are not marked as such. Document name Document No. V850ES User’s Manual Architecture U15943EJ3V0UM00 Self-Programming Application Note U16929EE3V0AN00 Refer to http://www.eu.necel.com/docuweb/ to obtain the latest version of above documents. Further information For further information see http://www.ee.nec.de. User’s Manual U18743EE1V2UM00...
Page 9: Table Of Contents
Table of Contents Chapter 1 Introduction ..........19 General .
Page 10 Table of Contents 2.4.24 Port type F100x-U ..........74 2.4.25 Port type F1010-U.
Page 11 Table of Contents Chapter 3 CPU System Functions ....... 135 Overview.
Page 12 Table of Contents Non-Maskable Interrupts ..........224 5.2.1 Operation .
Page 13 Table of Contents 7.5.1 PRDSELH register - Product selection code register High ... . . 288 Chapter 8 Data Protection and Security ......289 Overview.
Page 14 Table of Contents 13.3 Control Registers ..........381 13.4 Operation .
Page 15 Table of Contents Chapter 17 I C Bus (IIC) ..........457 17.1 Features .
Page 16 Table of Contents 18.3.5 CAN sleep mode/CAN stop mode function ......542 18.3.6 Error control function......... . 542 18.3.7 Baud rate control function .
Page 17 Table of Contents 19.3 ADC Registers ........... . . 667 19.4 Operation .
Page 18 Table of Contents Appendix A Special Function Registers ......737 CAN Registers ........... . . 737 Other Special Function Registers .
Page 19: Chapter 1 Introduction
Chapter 1 Introduction The V850ES/Fx3-L is a product line in NEC Electronics’ V850 family of single- chip microcontrollers designed for automotive applications. 1.1 General The V850ES/Fx3-L single-chip microcontroller devices make the performance gains attainable with 32-bit RISC-based controllers available for embedded control applications.
Page 20: Features Summary
Chapter 1 Introduction A full range of software development tools A development system is available that includes an optimized C compiler, debugger, in-circuit emulator, simulator, system performance analyzer, and other elements. 1.2 Features Summary The V850ES/Fx3-L series includes the following microcontrollers: •...
Page 21 Introduction Chapter 1 User’s Manual U18743EE1V2UM00...
Page 22 Chapter 1 Introduction User’s Manual U18743EE1V2UM00...
Page 23: Description
Introduction Chapter 1 1.3 Description The following figure provides a functional block diagram of the V850ES/FE3-L, V850ES/FF3-L, and V850ES/FG3-L microcontrollers. Power and Reset Interrupt INTP0 to INTP7 Controller Note 1 INTP8 to INTP11 Reset Low Voltage Detector Power supply KR0 to KR7 Key Interrupt Memory Access Note 4...
Page 24 Chapter 1 Introduction Table 1-2 on page 24 summarizes the different features of the V850ES/FE3-L, V850ES/FF3-L, V850ES/FG3-L series devices, marked as “Notes” in Figure 1-1 on page 23. Table 1-2 V850ES/FE3-L, V850ES/FF3-L, V850ES/FG3-L feature set differences V850ES/FE3-L V850ES/FF3-L V850ES/FG3-L Note Feature √...
Page 25: Internal Units
Introduction Chapter 1 1.3.1 Internal units The CPU can execute almost all instruction processing, such as address calculation, arithmetic and logic operations, and data transfer, in one clock under control of a five-stage pipeline. Dedicated hardware units such as a multiplier and a 32-bit barrel shifter are provided to speed up complicated instruction processing.
Page 26 Chapter 1 Introduction • Core functions “Pin Functions” on page 31 “CPU System Functions” on page 135 “Clock Generator” on page 179 “Interrupt Controller (INTC)” on page 221 “Key Interrupt Function” on page 257 • Memory access “Flash Memory” on page 259 •...
Page 27: Ordering Information
Introduction Chapter 1 1.4 Ordering Information 1.4.1 V850ES/FE3-L ordering information On-chip Quality Part number Package flash Remark grade memory UPD70F3610M1GBA-GAH-AX 64-pin plastic LQFP 64 KB without Power-On- (0.5mm, 10 x 10 mm Clear circuit UPD70F3610M1GBA1-GAH-AX UPD70F3610M1GBA2-GAH-AX UPD70F3610M2GBA-GAH-AX with Power-On- Clear circuit UPD70F3610M2GBA1-GAH-AX UPD70F3610M2GBA2-GAH-AX UPD70F3610M1GAA-GAN-AX...
Page 28 Chapter 1 Introduction On-chip Quality Part number Package flash Remark grade memory UPD70F3613M1GBA-GAH-AX 64-pin plastic LQFP 192KB without Power-On- (0.5mm, 10 x 10 mm Clear circuit UPD70F3613M1GBA1-GAH-AX UPD70F3613M1GBA2-GAH-AX UPD70F3613M2GBA-GAH-AX with Power-On- Clear circuit UPD70F3613M2GBA1-GAH-AX UPD70F3613M2GBA1-GAH-AX UPD70F3614M1GBA-GAH-AX 256KB without Power-On- Clear circuit UPD70F3614M1GBA1-GAH-AX UPD70F3614M1GBA2-GAH-AX UPD70F3614M2GBA-GAH-AX...
Page 29: V850Es/Ff3-L Ordering Information
Introduction Chapter 1 1.4.2 V850ES/FF3-L ordering information On-chip Quality Part number Package flash Remark grade memory UPD70F361M1GBA-GAH-AX 80-pin plastic LQFP 64 KB without Power-On- (0.5mm, 12 x 12 mm Clear circuit UPD70F3615M1GBA1-GAH-AX UPD70F3615M1GBA2-GAH-AX UPD70F3615M2GBA-GAH-AX with Power-On- Clear circuit UPD70F3615MGBA1-GAH-AX UPD70F3615M2GBA2-GAH-AX UPD70F3616M1GBA-GAH-AX 96 KB without Power-On-...
Page 30: V850Es/Fg3-L Ordering Information
Chapter 1 Introduction 1.4.3 V850ES/FG3-L ordering information On-chip Quality Part number Package flash Remark grade memory UPD70F3620M1GBA-GAH-AX 100-pin plastic LQFP 128 KB without Power-On- (0.5mm, 14 x 14 mm Clear circuit UPD70F3620M1GBA1-GAH-AX UPD70F3620M1GBA2-GAH-AX UPD70F3620M2GBA-GAH-AX with Power-On- Clear circuit UPD70F3620M2GBA1-GAH-AX UPD70F3620M2GBA2-GAH-AX UPD70F3621M1GBA-GAH-AX 192KB without Power-On-...
Page 31: Chapter 2 Pin Functions
Chapter 2 Pin Functions This chapter lists the ports of the microcontroller. It presents the configuration of the ports for alternative functions. Noise elimination on input signals is explained and a recommendation for the connection of unused pins is given at the end of the chapter.
Page 32: Description
Chapter 2 Pin Functions 2.1.1 Description The V850ES/FE3-L, V850ES/FF3-L, and V850ES/FG3-L microcontrollers have the port groups shown below. Port group 0 P913 Port group 9 FG3-L Port group 1 P915 only FG3-L only P910 P912 FG3-L Port group 3 only PCM0 FF3-L/FG3-L PCM1...
Page 33 Pin Functions Chapter 2 Port group overview Table 2-1 gives an overview of the port groups. For each port group it shows the supported functions in port mode and in alternative mode. Any port group can operate in 8-bit or 1-bit units. Port groups 3, 6, 9 and DL can additionally operate in 16-bit units.
Page 34 Chapter 2 Pin Functions “Port Type Diagrams” on page 51. User’s Manual U18743EE1V2UM00...
Page 35: Terms
Pin Functions Chapter 2 2.1.2 Terms In this section, the following terms are used: • Pin Denotes the physical pin. Every pin is uniquely denoted by its pin number. A pin can be used in several modes. Depending on the selected mode, a pin name is allocated to the pin.
Page 36: Port Group Configuration Registers
Chapter 2 Pin Functions 2.2 Port Group Configuration Registers This section starts with an overview of all configuration registers and then presents all registers in detail. The configuration registers are classified in the following groups: • “Pin function configuration” on page 37 •...
Page 37: Pin Function Configuration
Pin Functions Chapter 2 2.2.2 Pin function configuration The registers for pin function configuration define the general function of a pin: • port mode or alternative mode • in port mode: input mode or output mode • in alternative mode: selection of one of the alternative functions in alternative mode •...
Page 38 Chapter 2 Pin Functions PMCn - Port mode control register The PMCn register specifies whether the individual pins of port group n are in port mode or in alternative mode. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register.
Page 39 Pin Functions Chapter 2 PMn - Port mode register The PMn register specifies whether the individual pins of the port group n are in input mode or in output mode. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register.
Page 40 Chapter 2 Pin Functions PFCn - Port function control register If a pin is in alternative mode (PMCn.PMCnm = 1) some pins offer up to four alternative functions. The PFCn register together with the PFCEn register specifies which function of a pin is to be used.
Page 41 Pin Functions Chapter 2 PFCEn - Port function control expansion register If a pin is in alternative mode (PMCn.PMCnm = 1) some pins offer up to four alternative functions. The PFCEn together with the PFCn register specifies which function of a pin is to be used.
Page 42 Chapter 2 Pin Functions OCDM - On-chip debug mode register The 8-bit OCDM register specifies whether dedicated pins of the microcontroller operate in normal operation mode or can be used for on-chip debugging (N-Wire interface). The setting of this register concerns only those pins that can be used for the N-Wire interface: P05/DRST, P52/DDI, P53/DDO, P54/DCK, and P55/DMS.
Page 43: Pin Data Input/Output
Pin Functions Chapter 2 2.2.3 Pin data input/output If a pin is in port mode, the registers for pin data input/output specify the input and output data. Pn - Port register If a pin is in port mode (PMCn.PMCnm = 0), data is input from or output to an external device by writing or reading the Pn register.
Page 44 Chapter 2 Pin Functions Alternative mode In alternative mode (PMCn.PMCnm = 1), the corresponding port type defines whether a pin is in input or output mode. However, register PMn influences the writing/reading of register Pn. In alternative mode, data is written to or read from the Pn register as follows: Table 2-11 Writing/reading register Pn in alternative mode (PMCn.PMCnm = 1) Function...
Page 45: Configuration Of Pull-Up Resistors
Pin Functions Chapter 2 2.2.4 Configuration of pull-up resistors PUn - Port pull-up resistor option register The PUn register specifies whether a pull-up resistor is connected to the pin. Access This register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units.
Page 46: Open Drain Configuration
Chapter 2 Pin Functions 2.2.5 Open drain configuration PFn - Port function register If a pin is in alternative mode (PMCn.PMCnm = 1), the PFn register specifies normal output or open-drain output. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register.
Page 47: Port Buffers Diagrams
Pin Functions Chapter 2 2.3 Port Buffers Diagrams This chapter presents the block diagrams of all buffer types. The tables in “Port group configuration lists” on page 100 informs also about the buffer type, used for each port. Buffer type 2 Figure 2-2 Block diagram: buffer type 2 Buffer type 5...
Page 48 Chapter 2 Pin Functions Buffer type 5-AF Figure 2-4 Block diagram: buffer type 5-AF Buffer type 5-K Figure 2-5 Block diagram: buffer type 5-K User’s Manual U18743EE1V2UM00...
Page 49 Pin Functions Chapter 2 Buffer type 5-W Figure 2-6 Block diagram: buffer type 5-W Buffer type 11-G Figure 2-7 Block diagram: buffer type 11-G User’s Manual U18743EE1V2UM00...
Page 50 Chapter 2 Pin Functions Buffer type 16 Figure 2-8 Block diagram: buffer type 16 User’s Manual U18743EE1V2UM00...
Page 51: Port Type Diagrams
Pin Functions Chapter 2 2.4 Port Type Diagrams This chapter presents the block diagrams of all port types. The tables in the detailed descriptions of each port group from “Port group 0” on page 108 onwards informs also about the port type, used for each port. 2.4.1 Port type C PMmn (a) Output buffer control...
Page 52: Port Type C-U
Chapter 2 Pin Functions 2.4.2 Port type C-U EVDD PUmn (c) Pull-up control PMmn (a) Output buffer control PORT Address (b) Input buffer control Figure 2-10 Port type C-U block diagram User’s Manual U18743EE1V2UM00...
Page 53: Port Type D0
Pin Functions Chapter 2 2.4.3 Port type D0 PMCmn (a) Output buffer control PMmn 1st alternate function PORT (d) Output data Selection Address (b) Input buffer control Figure 2-11 Port type D0 block diagram User’s Manual U18743EE1V2UM00...
Page 54: Port Type D0-U
Chapter 2 Pin Functions 2.4.4 Port type D0-U EVDD PUmn (c) Pull-up control PMCmn (a) Output buffer control PMmn 1st alternate function PORT (d) Output data Selection Address (b) Input buffer control Figure 2-12 Port type D0-U block diagram User’s Manual U18743EE1V2UM00...
Page 55: Port Type D1
Pin Functions Chapter 2 2.4.5 Port type D1 PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input control 1st alternate f unction Figure 2-13 Port type D1 block diagram User’s Manual U18743EE1V2UM00...
Page 56: Port Type D1-U
Chapter 2 Pin Functions 2.4.6 Port type D1-U EVDD PUmn (c) Pull-up control PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input control 1st alternate f unction Figure 2-14 Port type D1-U block diagram User’s Manual U18743EE1V2UM00...
Page 57: Port Type D1-Ui
Pin Functions Chapter 2 2.4.7 Port type D1-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input Edge Noise control 1st alternate f unction detector remov al Figure 2-15...
Page 58: Port Type D3-Ui
Chapter 2 Pin Functions 2.4.8 Port type D3-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input Edge Noise control 1st alternate f unction detector remov al (INTPx)
Page 59: Port Type D1A
Pin Functions Chapter 2 2.4.9 Port type D1A PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control 1st alternate function Figure 2-17 Port type D1A block diagram User’s Manual U18743EE1V2UM00...
Page 60: Port Type D1O1-Ui
Chapter 2 Pin Functions 2.4.10 Port type D1O1-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn OCDM OCDM0 PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input Edge Noise control 1st alternate f unction detector remov al (f) On-chip debug...
Page 61: Port Type D2
Pin Functions Chapter 2 2.4.11 Port type D2 Output enable signal 1 in alternative mode PM C PMCmn (a) Output buffer control PMmn 1st alternate f unction PORT (d) Output data Selection Address (b) Input buffer control Input enable signal 1 (e) A lternate function input in alternative mode control...
Page 62: Port Type E01-U
Chapter 2 Pin Functions 2.4.12 Port type E01-U EVDD PUmn (c) Pull-up control PFCmn PMCmn (a) Output buffer control PMmn 1st alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input control 2nd alternate f unction Figure 2-20 Port type E01-U block diagram User’s Manual U18743EE1V2UM00...
Page 63: Port Type E10-U
Pin Functions Chapter 2 2.4.13 Port type E10-U EVDD PUmn (c) Pull-up control PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input control 1st alternate f unction Figure 2-21 Port type E10-U block diagram User’s Manual U18743EE1V2UM00...
Page 64: Port Type E10-Ui
Chapter 2 Pin Functions 2.4.14 Port type E10-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input Edge Noise control...
Page 65: Port Type E11-U
Pin Functions Chapter 2 2.4.15 Port type E11-U EVDD PUmn (c) Pull-up control PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input 1st alternate function control 2nd alternate function Figure 2-23 Port type E11-U block diagram User’s Manual U18743EE1V2UM00...
Page 66: Port Type E11-Ui
Chapter 2 Pin Functions 2.4.16 Port type E11-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control Edge Noise (e) Alternate function input 1st alternate function detector removal control 2nd alternate function...
Page 67: Port Type E21-U
Pin Functions Chapter 2 2.4.17 Port type E21-U EVDD PUmn (c) Pull - up control P ch Output enable signal 1 in alternative mode P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 1st alternate function PORT (d) Output data Selection Address (b) Input buffer control (e) A lternate function input...
Page 68: Port Type Ex0-U
Chapter 2 Pin Functions 2.4.18 Port type Ex0-U EVDD PUmn (c) Pull-up control PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate function PORT (d) Output data Selection Address (b) Input buffer control Figure 2-26 Port type Ex0-U block diagram User’s Manual U18743EE1V2UM00...
Page 69: Port Type Ex1-U
Pin Functions Chapter 2 2.4.19 Port type Ex1-U EVDD PUmn (c) Pull-up control PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input control 2nd alternate f unction Figure 2-27 Port type Ex1-U block diagram User’s Manual U18743EE1V2UM00...
Page 70: Port Type Ex1-Ui
Chapter 2 Pin Functions 2.4.20 Port type Ex1-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input Edge Noise control 2nd alternate f unction detector remov al Figure 2-28...
Page 71: Port Type Ex2-U
Pin Functions Chapter 2 2.4.21 Port type Ex2-U EVDD PUmn (c) Pull - up control P ch Output enable signal 2 in alternative mode P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 2nd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control...
Page 72: Port Type F010X-U
Chapter 2 Pin Functions 2.4.22 Port type F010x-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 1st alternate f unction 3rd alternate f unction (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input control 2nd alternate f unction...
Page 73: Port Type F010X-Ui
Pin Functions Chapter 2 2.4.23 Port type F010x-UI EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 1st alternate f unction 3rd alternate f unction (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input control 2nd alternate f unction...
Page 74: Port Type F100X-U
Chapter 2 Pin Functions 2.4.24 Port type F100x-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate f unction 3rd alternate f unction (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input control 1st alternate f unction...
Page 75: Port Type F1010-U
Pin Functions Chapter 2 2.4.25 Port type F1010-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate function 4th alternate function (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input 1st alternate function control 3rd alternate function...
Page 76: Port Type F101X-U
Chapter 2 Pin Functions 2.4.26 Port type F101x-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input 1st alternate f unction control 3rd alternate f unction...
Page 77: Port Type F1100O0-U
Pin Functions Chapter 2 2.4.27 Port type F1100O0-U EVDD PUmn (c) Pull-up control OCDM signal PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 3rd alternate function 4th alternate function On-chip debug function (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input 1st alternate function control...
Page 78: Port Type F1100O1-U
Chapter 2 Pin Functions 2.4.28 Port type F1100O1-U EVDD PUmn (c) Pull-up control OCDM signal PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 3rd alternate function 4th alternate function (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input 1st alternate function control...
Page 79: Port Type F1100-U
Pin Functions Chapter 2 2.4.29 Port type F1100-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 3rd alternate function 4th alternate function (d) Output data Selection PORT Address (b) Input buffer control (e) 1st alternate function input 1st alternate function control 2nd alternate function...
Page 80: Port Type F1110-Ui
Chapter 2 Pin Functions 2.4.30 Port type F1110-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 4th alternate function PORT (d) Output data Selection Address (b) Input buffer control Edge Noise 1st alternate function (e) Alternate function input...
Page 81: Port Type F113X-Ui
Pin Functions Chapter 2 2.4.31 Port type F113x-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control 1st alternate function (e) Alternate function input 2nd alternate function control Edge Noise...
Page 82: Port Type F1X10-Ui
Chapter 2 Pin Functions 2.4.32 Port type F1x10-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 4th alternate f unction PORT (d) Output data Selection Address (b) Input buffer control Edge Noise (e) Alternate function input...
Page 83: Port Type F3X1X-Ui
Pin Functions Chapter 2 2.4.33 Port type F3x1x-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control Edge Noise 1st alternate f unction detector remov al (INTPx) (e) Alternate function input control...
Page 84: Port Type F1Xx0O1-U
Chapter 2 Pin Functions 2.4.34 Port type F1xx0O1-U EVDD PUmn (c) Pull-up control OCDM signal PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 4th alternate function PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input control 1st alternate function On-chip debug function...
Page 85: Port Type Fx010-U
Pin Functions Chapter 2 2.4.35 Port type Fx010-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate f unction 4th alternate f unction (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input control 3rd alternate f unction...
Page 86: Port Type Fx01X-U
Chapter 2 Pin Functions 2.4.36 Port type Fx01x-U EVDD PUmn (c) Pull - up control P ch P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 2nd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) A lternate function input...
Page 87: Port Type Fx103-Ui
Pin Functions Chapter 2 2.4.37 Port type Fx103-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 3rd alternate function PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input Edge Noise Share...
Page 88: Port Type Fx10X-U
Chapter 2 Pin Functions 2.4.38 Port type Fx10x-U EVDD PUmn (c) Pull - up control P ch P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 2nd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) A lternate function input...
Page 89: Port Type Fx10X-Ui
Pin Functions Chapter 2 2.4.39 Port type Fx10x-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 3rd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input Edge Noise...
Page 90: Port Type Fx110-U
Chapter 2 Pin Functions 2.4.40 Port type Fx110-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 4th alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input 2nd alternate f unction control 3rd alternate f unction...
Page 91: Port Type Fx120-Ufi
Pin Functions Chapter 2 2.4.41 Port type Fx120-UFI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 3rd alternate f unction 4th alternate f unction (d) Output data Selection PORT Address (b) Input buffer control Edge...
Page 92: Port Type Fx123-Ufi
Chapter 2 Pin Functions 2.4.42 Port type Fx123-UFI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 3rd alternate function PORT (d) Output data Selection Address (b) Input buffer control Edge Noise Share...
Page 93: Port Type Fx12X-Ufi
Pin Functions Chapter 2 2.4.43 Port type Fx12x-UFI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 3rd alternate function PORT (d) Output data Selection Address (b) Input buffer control Edge Noise (e) Alternate function input...
Page 94: Port Type Fx13X-U
Chapter 2 Pin Functions 2.4.44 Port type Fx13x-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input Share 2nd & 3rd alternate function control control (KRx) 3rd alternate function (RXDDy)
Page 95: Port Type Fx210-U
Pin Functions Chapter 2 2.4.45 Port type Fx210-U EVDD PUmn (c) Pull - up control P ch Output enable signale 2 in alternative mode P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 2nd alternate function 4th alternate function (d) Output data Selection PORT...
Page 96: Port Type Fx2X0-U
Chapter 2 Pin Functions 2.4.46 Port type Fx2x0-U EVDD PUmn (c) Pull - up control P ch Output enable signale 2 in alternative mode P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 2nd alternate f unction 4th alternate f unction (d) Output data Selection PORT...
Page 97: Port Type Fxx10-U
Pin Functions Chapter 2 2.4.47 Port type Fxx10-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 4th alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input control 3rd alternate f unction Figure 2-55...
Page 98: Port Type Fxx1X-U
Chapter 2 Pin Functions 2.4.48 Port type Fxx1x-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input control 3rd alternate f unction Figure 2-56 Port type Fxx1x-U block diagram User’s Manual U18743EE1V2UM00...
Page 99: Port Type Fxx2X-U
Pin Functions Chapter 2 2.4.49 Port type Fxx2x-U EVDD PU mn (c) Pull - up control P ch Output enable signale 3 in alternative mode P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 3rd alternate f unction PORT (d) Output data Selection Address...
Page 100: Port Group Configuration
Chapter 2 Pin Functions 2.5 Port Group Configuration This section provides an overview of the port groups (Table 2-14) and of the pin functions (Table 2-14 on page 100). In Table 2-40 on page 130 it is listed how the pin functions change if the microcontroller is reset. In the subsections, for every port group the settings of the configuration registers is listed.
Page 101 Pin Functions Chapter 2 Table 2-14 V850ES/FE3-L, V850ES/FF3-L, V850ES/FG3-L port group list (2/3) Port group Port Buffer Alternative outputs Alternative inputs name name type – ANI0 11-G – ANI1 11-G – ANI2 11-G – ANI3 11-G – ANI4 11-G – ANI5 11-G –...
Page 102 Chapter 2 Pin Functions Table 2-14 V850ES/FE3-L, V850ES/FF3-L, V850ES/FG3-L port group list (3/3) Port group Port Buffer Alternative outputs Alternative inputs name name type PCT0 – – PCT1 – – PCT4 – – PCT6 – – PDL0 – – PDL1 –...
Page 103 Pin Functions Chapter 2 User’s Manual U18743EE1V2UM00...
Page 104: Alphabetic Pin Function List
Chapter 2 Pin Functions 2.5.2 Alphabetic pin function list Table 2-15 provides a list of all pin function names in alphabetic order. The table does not list differences between the various devices of the V850ES/ Fx3-L. These are listed in Table 2-14 on page 100. Table 2-15 Alphabetic pin functions list (1/3) Pin number...
Page 105 Pin Functions Chapter 2 Table 2-15 Alphabetic pin functions list (2/3) Pin number Pin name Pin function Port FE3 FF3 FG3 FLMD0 – Flash programming mode setting pin – FLMD1 Flash programming mode setting pin PDL5 INTP0 External interrupts INTP0 - INTP10 INTP1 INTP2 INTP3...
Page 106 Chapter 2 Pin Functions Table 2-15 Alphabetic pin functions list (3/3) Pin number Pin name Pin function Port FE3 FF3 FG3 TIAA00 Timer TAA channel 0 capture trigger input TIAA10 TIAA20 TIAA30 TIAA40 TIAA01 Timer TAA channel 1 capture trigger input TIAA11 TIAA21 TIAA31...
Page 107 Pin Functions Chapter 2 Note The following alternative functions are provided on two pins each: Unit Alternative function Port 1 Port 2 Timer TOAA01 CTXD0 CRXD0 Key interrupt Thus you can select on which pin the alternative function should appear. Refer to “Pin function configuration”...
Page 108: Port Group 0
Chapter 2 Pin Functions 2.5.3 Port group 0 Port group 0 is a 7-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP0 to INTP3) • Non-maskable interrupt (NMI) • N-Wire debug interface reset (DRST) •...
Page 109 Pin Functions Chapter 2 Table 2-17 Port group 0: configuration registers Initial Register Address Used bits value PMC0 FFFF F440 PMC06 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00 FFFF F420 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PFC0 FFFF F460 PFC06 PFC04 PFC03 PFC02...
Page 110: Port Group 1 (V850Es/Fg3-L)
Chapter 2 Pin Functions 2.5.4 Port group 1 (V850ES/FG3-L) Note Port group 1 is available only for V850ES/FG3-L. Port group 1 is a 2-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP9 and INTP10) Port group 1 includes the following pins: Table 2-18 Port group 1: pin functions and buffer types...
Page 111: Port Group 3
Pin Functions Chapter 2 2.5.5 Port group 3 Port group 3 is a 10-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP7 and INTP8) • Timer TAA0 channels (TIAA00, TIAA01 and TOAA00, TOAA01) •...
Page 112 Chapter 2 Pin Functions Table 2-21 Port group 3: configuration registers Initial Register Address Used bits value V850ES/FE3-L PMC3L FFFF F446 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PM3L FFFF F426 PM35 PM34 PM33 PM32 PM31 PM30 PFC3L FFFF F466 PFC35 PFC34 PFC33 PFC32...
Page 113: Port Group 4
Pin Functions Chapter 2 2.5.6 Port group 4 Port group 4 is a 3-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP14) • Key interrupt input (KR0 to KR2) • Clocked Serial Interface CSIB0 data/clock line (SIB0, SOB0, SCKB0) Port group 4 includes the following pins: Table 2-22 Port group 4: pin functions and buffer...
Page 114: Port Group 5
Chapter 2 Pin Functions 2.5.7 Port group 5 Port group 5 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Key interrupt input 0 to 5 (KR0 to KR5) • N-Wire debug interface signals (DDI, DDO, DCK, DMS) Port group 5 includes the following pins: Table 2-24 Port group 5: pin functions and buffer types...
Page 115 Pin Functions Chapter 2 Table 2-25 Port group 5: configuration registers Register Address Initial value Used bits PMC5 FFFF F44A PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 FFFF F42A PM55 PM54 PM53 PM52 PM51 PM50 OCDM FFFF F9FC / 01 OCDM0 FFFF F40A undefined FFFF FC4A...
Page 116: Port Group 7
Chapter 2 Pin Functions 2.5.8 Port group 7 Port group 7 is a 16-bit port group. It includes pins for the following functions: • A/D Converter 0 inputs Port group 7 includes the following pins: Table 2-26 Port group 7: pin functions and buffer types Pin functions in different modes Port Noise...
Page 117 Pin Functions Chapter 2 Table 2-27 Port group 7: configuration registers Initial Register Address Used bits value PMC7L FFFF F44E PMC77 PMC76 PMC75 PMC74 PMC73 PMC72 PMC71 PMC70 PMC7H FFFF F44F PMC715 PMC714 PMC713 PMC712 PMC711 PMC710 PMC79 PMC78 PM7L FFFF F42E PM77 PM76...
Page 118: Port Group 9
Chapter 2 Pin Functions 2.5.9 Port group 9 Port group 9 is an 16-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP4 to INTP6) • Key interrupt input 6 to 7 (KR6 to KR7) •...
Page 119 Pin Functions Chapter 2 Table 2-28 Port group 9: pin functions and buffer types Pin functions in different modes Port mode Alternative mode (PMCnm = 0) (PMCnm = 1) function Port Noise Input after type filter charact. PFCE = 0 PFCE = 1 reset Function 1...
Page 120 Chapter 2 Pin Functions Table 2-29 Port group 9: V850ES/FE3-L, V850ES/FF3-L configuration registers Initial Register Address Used bits value PMC9L FFFF F452 PMC97 PMC96 PMC91 PMC90 PMC9H FFFF F453 PMC915 PMC914 PMC913 PMC99 PMC98 PMC9 (16 bit) FFFF F452 0000 PMC915 to PMC98 (PMC9H) PMC97 to PMC90 (PMC9L) PM9L...
Page 121 Pin Functions Chapter 2 Table 2-30 Port group 9: V850ES/FG3-L configuration registers Initial Register Address Used bits value PMC9L FFFF F452 PMC97 PMC96 PMC91 PMC90 PMC9H FFFF F453 PMC915 PMC914 PMC913 PMC99 PMC98 PMC9 (16 bit) FFFF F452 0000 PMC915 to PMC98 (PMC9H) PMC97 to PMC90 (PMC9L) PM9L FFFF F432...
Page 122: Port Group Cm
Chapter 2 Pin Functions 2.5.10 Port group CM Port group CM is a 6-bit port group. In alternative mode, it comprises pins for the following functions: • CPU system clock output (CLKOUT) Port group CM includes the following pins: Table 2-31 Port group CM: pin functions and buffer types Pin functions in different modes Port...
Page 123: Port Group Cs (V850Es/Ff3-L, V850Es/Fg3-L)
Pin Functions Chapter 2 2.5.11 Port group CS (V850ES/FF3-L, V850ES/FG3-L) Note Port group CS is available only for V850ES/FF3-L, V850ES/FG3-L Port group CS is an 8-bit port group. In alternative mode, it comprises pins for the following functions: Port group CS includes the following pins: Table 2-33 Port group CS: pin functions and buffer types Pin functions in different modes...
Page 124: Port Group Ct (V850Es/Ff3-L, V850Es/Fg3-L)
Chapter 2 Pin Functions 2.5.12 Port group CT (V850ES/FF3-L, V850ES/FG3-L) Note Port group CT is available only for V850ES/FF3-L, V850ES/FG3-L. Port group CT is an 8-bit port group. In alternative mode, it comprises pins for the following functions: Port group CT includes the following pins: Table 2-35 Port group CT: pin functions and buffer types Pin functions in different modes...
Page 125: Port Group Dl
Pin Functions Chapter 2 2.5.13 Port group DL Port group DL is an 16-bit input/output port group. Port group DL includes the following pins: Table 2-37 Port group DL: pin functions and buffer types Pin functions in different modes Port Noise Input function...
Page 126: Noise Elimination
Chapter 2 Pin Functions 2.6 Noise Elimination The input signals at some pins are passing a filter to remove noise and glitches. The microcontroller supports both analog and digital filters. In Table 2-16 on page 108 and in the following tables it is listed whether a pin is equipped with an analog filter, a digital filter, both analog and digital filter, or no filter at all.
Page 127: Digitally Filtered Inputs
Pin Functions Chapter 2 2.6.2 Digitally filtered inputs The input signal INTP3 is passed through both an analog and a digital filter. The digital filter operates in all modes, in which fXX is available. Thus, it does not operate in standby modes (if fXT is used as the sampling clock, it can operate in standby modes).
Page 128 Chapter 2 Pin Functions NFC - Digital noise filter control register The 8-bit NFC register specifies the noise elimination circuit for signal INTP3. Access This register can be read/written in 8-bit and 1-bit units. Address FFFF F318 Initial Value . This register is cleared by any reset. NFEN NFSTS NFC2...
Page 129 Pin Functions Chapter 2 DMA functions. When using the interrupt function, after the N sampling clocks (selected sampling frequency N = 3 or 2) have elapsed, enable interrupts after the interrupt request flag (PIC3.PIF3 bit) has been cleared. When using the DMA function (started by INTP3), enable DMA after the N sampling clocks have elapsed.
Page 130: Pin Functions In Reset And Power Save Modes
Chapter 2 Pin Functions 2.7 Pin Functions in Reset and Power Save Modes The following table summarizes the status of the pins during reset and power save modes and after release of these operating states in normal operation mode. The reset source makes a difference concerning the N-Wire debugger interface pins DRST, DDI, DDO, DCK and DMS after reset release.
Page 131: Recommended Connection Of Unused Pins
Pin Functions Chapter 2 2.8 Recommended Connection of unused Pins If a pin is not used, it is recommended to connect it as follows: Table 2-41 Recommended connection of unused pins Recommended connection Port pins pins of port groups 0, 1, 3 to 5, 9 •...
Page 132: Package Pins Assignment
Chapter 2 Pin Functions 2.9 Package Pins Assignment The following figures shows the location of pins in top view. Every pin is labelled with its pin number and all possible pin names. 2.9.1 V850ES/FE3-L package pins assignment AVREF0 ○ 48 ←→○ PDL1 AVSS ○...
Page 133: V850Es/Ff3-L Package Pins Assignment
Pin Functions Chapter 2 2.9.2 V850ES/FF3-L package pins assignment AVREF0 60 ←→○ PDL3 ○ AVSS ○ 59 ←→○ PDL2 P00/TIAA31/TOAA31 ○←→ 58 ←→○ PDL1 P01/TIAA30/TOAA30 ○←→ 57 ←→○ PDL0 P02/NMI/TIAA40/TOAA40 ○←→ 56 ←→○ PCT6 P03/INTP0/ADTRG/TIAA41/TOAA41 ○←→ 55 ←→○ PCT4 µPD70F3615GK-GAK P04/INTP1/CRXD0 ○←→...
Page 134: V850Es/Fg3-L Package Pins Assignment
Chapter 2 Pin Functions 2.9.3 V850ES/FG3-L package pins assignment AVREF0 ○ 75 ←→○ PDL4 AVSS ○ 74 ←→○ PDL3 P10/INTP9 ○←→ 73 ←→○ PDL2 P11/INTP10 ○←→ 72 ←→○ PDL1 EVDD ○ 71 ←→○ PDL0 P00/TIAA31/TOAA31 ○←→ ○ BVDD P01/TIAA30/TOAA30 ○←→ ○...
Page 135: Chapter 3 Cpu System Functions
Chapter 3 CPU System Functions This chapter describes the registers of the CPU, the operation modes, the address space and the memory areas. 3.1 Overview The CPU is founded on Harvard architecture and it supports a RISC instruction set. Basic instructions can be executed in one clock period. Optimized five- stage pipelining is supported.
Page 136: Description
Chapter 3 CPU System Functions 3.1.1 Description The figure below shows a block diagram of the microcontroller, focusing on the CPU and modules that interact with the CPU directly. Table 3-1 lists the bus types. RCU interface System controller Instruction queue Multiplier (16 x 16 ? 32) Program counter...
Page 137: Cpu Register Set
CPU System Functions Chapter 3 3.2 CPU Register Set There are two categories of registers: • General purpose registers • System registers All registers are 32-bit registers. An overview is given in the figure below. For details, refer to V850ES User’s Manual Architecture. EIPC (Status Saving Register during interrupt) (Zero Register)
Page 138: General Purpose Registers (R0 To R31)
Chapter 3 CPU System Functions 3.2.1 General purpose registers (r0 to r31) Each of the 32 general purpose registers can be used as a data variable or address variable. However, the registers r0, r1, r3 to r5, r30, and r31 may implicitly be used by the assembler/compiler (see table Table 3-2).
Page 139: System Register Set
CPU System Functions Chapter 3 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Additionally, the program counter holds the instruction address during program execution. To read/write the system registers, use instructions LDSR (load to system register) or STSR (store contents of system register), respectively, with a specific system register number (regID) indicated below.
Page 140 Chapter 3 CPU System Functions PC - Program counter The program counter holds the instruction address during program execution. The lower 26 bits are valid, and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to 26, it is ignored. Branching to an odd address cannot be performed.
Page 141 CPU System Functions Chapter 3 PSW - Program status word The 32-bit program status word is a collection of flags that indicates the status of the program (result of instruction execution) and the status of the CPU. If the bits in the register are modified by the LDSR instruction, the PSW will take on the new value immediately after the LDSR instruction has been executed.
Page 142 Chapter 3 CPU System Functions Table 3-5 PSW register contents (2/2) Bit position Flag Function Overflow flag. Indicates whether an overflow occurred as a result of the operation. 0: Overflow did not occur. 1: Overflow occurred. Sign flag. Indicates whether the result of the operation is negative. 0: Result is positive or zero.
Page 143 CPU System Functions Chapter 3 EIPSW, FEPSW, DBPSW, CTPSWPSW saving registers The PSW saving registers save the contents of the program status word for different occasions, see Table 3-4. When one of the occasions listed in Table 3-4 occurs, the current value of the PSW is saved to the saving registers.
Page 144 Chapter 3 CPU System Functions ECR - Interrupt/exception source register The 32-bit ECR register displays the exception codes if an exception or an interrupt has occurred. With the exception code, the interrupt/exception source can be identified. For a list of interrupts/exceptions and corresponding exception codes, see Table 3-9 on page 144.
Page 145 CPU System Functions Chapter 3 If an interrupt (maskable or non-maskable) is acknowledged during instruction execution, generally, the address of the instruction following the one being executed is saved to the saving registers, except when an interrupt is acknowledged during execution of one of the following instructions: •...
Page 146: Operation Modes
Chapter 3 CPU System Functions 3.3 Operation Modes This section describes the operation modes of the CPU and how the modes are specified. The following operation modes are available: • Normal operation mode • Flash programming mode After reset release, the microcontroller starts to fetch instructions from an internal boot ROM which contains the internal firmware.
Page 147: Address Space
CPU System Functions Chapter 3 Afterwards the software can be evaluated using breakpoints and the user resources (such as memory and I/O can be read or written. For more information see Chapter 23 on page 723. 3.4 Address Space In the following sections, the address space of the CPU is explained. Size and addresses of CPU address space and physical address space are explained.
Page 148 Chapter 3 CPU System Functions The 64 MB physical address space is seen as 64 images in the 4 GB CPU address space: CPU address space FFFF FFFFH Image FC00 0000H FBFF FFFFH Physical address space x3FF FFFFH Fixed peripheral I/O x3FF F000H Image note...
Page 149: Program And Data Space
CPU System Functions Chapter 3 3.4.2 Program and data space The CPU allows the following assignment of data and instructions to the CPU address space: • 4 GB as data space The entire CPU address space can be used for operand addresses. •...
Page 150 Chapter 3 CPU System Functions Wrap-around of data space If an operand address calculation exceeds 32 bits, only the lower 32 bits of the result are considered. Therefore, the addresses 0000 0000 and FFFF FFFF are contiguous addresses. This results in a wrap-around of the data space: Data space FFFF FFFEH FFFF FFFFH...
Page 151: Memory
CPU System Functions Chapter 3 3.5 Memory In the following sections, the memory of the CPU is introduced. Specific memory areas are described and a recommendation for the usage of the address space is given. 3.5.1 Memory areas The internal memory of the CPU provides several areas: •...
Page 152 Chapter 3 CPU System Functions Table 3-12 Internal RAM areas V850ES/Fx3-L Product Device RAM size Address range V850ES/FE3-L µPD70F3610 6 KB 03FF D800 – 03FF EFFF µPD70F3611 6 KB 03FF D800 – 03FF EFFF µPD70F3612 8 KB 03FF D000 – 03FF EFFF µPD70F3613 12 KB 03FF C000...
Page 153 CPU System Functions Chapter 3 For registers in which byte access is possible, if half word access is executed: • During read operation: The higher 8 bits become undefined. • During write operation: The lower 8 bits of data are written to the register.
Page 154: Recommended Use Of Data Address Space
Chapter 3 CPU System Functions 3.5.2 Recommended use of data address space When accessing operand data in the data space, one register has to be used for address generation. This register is called pointer register. With relative addressing, an instruction can access operand data at all addresses that lie in the range of ±32 KB relative to the address in the pointer register.
Page 155: Write Protected Registers
CPU System Functions Chapter 3 3.6 Write Protected Registers Write protected registers are protected from inadvertent write access due to erroneous program execution, etc. Write access to a write protected register is only given immediately after writing to a corresponding write enable register. For a write access to the write protected registers you have to use the following instructions: 1.
Page 156 Chapter 3 CPU System Functions Since any action between writing to a write enable register and writing to a protected register destroys this sequence, the effects of interrupts have to be considered: • Interrupts: In order to prevent any maskable interrupt to be acknowledged between the two write instructions in question, shield this sequence by DI-EI (disable interrupt—enable interrupt).
Page 157: Write Protection Control Registers
CPU System Functions Chapter 3 3.6.1 Write protection control registers The following section describes the registers that control access to write protected registers. PRCMD - Command register The 8-bit PRCMD register protects other registers from inadvertent write access, so that the system does not stop in case of a program hang-up. After writing to the PRCMD register, you are permitted to write once to one of the protected registers.
Page 158 Chapter 3 CPU System Functions User’s Manual U18743EE1V2UM00...
Page 159: Chapter 4 Clock Generator
Chapter 4 Clock Generator The Clock Generator provides the clock signals needed by the CPU and the on-chip peripherals. 4.1 Overview The Clock Generator can generate the required clock signals from the following sources: • Main oscillator—a built-in oscillator that requires an external crystal with a frequency between 4 MHz and 16 MHz •...
Page 160: Description
Chapter 4 Clock Generator 4.1.1 Description The Clock Generator is built up as illustrated in the following figure. OB_7A.STOPXTAL OB_7A.STOPRCZ PCC.FRC Xtal SubOSC WT, TMM0, TAA1, TAA3 240 KHz WDT2, TMM0 internal oscillator IDLE control RCM.RSTOP OB_7B.SUBCLK Clock Monitor PCC.MFRC IDLE1,2 mode OB_7B.PLLI[1:0] OB_7B.PLLO...
Page 161 Clock Generator Chapter 4 8 MHz internal The high speed internal oscillator generates a clock f with a frequency of oscillator typically 8 MHz. After reset release, the 8 MHz internal oscillator is activated. The high speed internal oscillator is equipped with a stop control. The oscillation can be stopped by means of the RCM register.
Page 162 Chapter 4 Clock Generator The clock sources MainOSC, PLL and 8 MHz internal oscillator can generate the master clock f . This clock forms the input to Prescaler2. Prescaler2 can divide the master clock f by 1, 2, 4, 8, 16 or 32. Its operation is set in the PCC register.
Page 163: Clock Monitor
Clock Generator Chapter 4 Clock for WDT2 This is the clock for the Watchdog Timer. The clock for WDT2 is available (and hence the Watchdog Timer running) as long as the chosen clock source (240 KHz internal oscillator or MainOSC) is active. Note that the WDT2 operation is defined in option byte 007A Stand-by control In the block diagram, you find also boxes labelled “IDLE Control”...
Page 164: Power Save Modes Overview
Chapter 4 Clock Generator 4.1.3 Power save modes overview The power consumption of the system can be effectively reduced by using the stand-by modes and selecting the appropriate mode for the application. The available stand-by modes are listed below. The following explanations provide a general overview. For details, please refer to “Power save modes description”...
Page 165: Start Conditions
Clock Generator Chapter 4 4.1.4 Start conditions After securing the setup time of the 8 MHz internal oscillator, the CPU begins program execution. The oscillation stabilization time for the internal oscillator is ensured by hardware. The table below shows the state during reset and after reset release. Table 4-2 Oscillation during reset period or after reset release Item...
Page 166: Clock Generator Registers
Chapter 4 Clock Generator 4.2 Clock Generator Registers The Clock Generator is controlled and operated by means of the following registers (the list is sorted according to memory allocation): Table 4-3 Clock Generator register overview Write- Register name Shortcut Address protected by register Power save control register...
Page 167 Clock Generator Chapter 4 The subsequent register descriptions are grouped as follows: • General clock generator registers: – “CCLS - CPU operation clock status register” on page 168 – “MCM - Main system clock mode register” on page 169 – “OSTC - Oscillation stabilization timer status register” on page 170 –...
Page 168: General Clock Generator Registers
Chapter 4 Clock Generator 4.2.1 General Clock Generator registers The general Clock Generator registers control and reflect the operation of the Clock Generator. CCLS - CPU operation clock status register The CCLS register indicates the CPU operation clock status. Access This register can be read in 1-bit or 8-bit units.
Page 169 Clock Generator Chapter 4 MCM - Main system clock mode register The 8-bit MCM register specifies the main system clock (f ) source in clock- through mode and informs about its status. Access This register can be read/written in 1-bit or 8-bit units. Writing to this register is protected by a special sequence of instructions.
Page 170 Chapter 4 Clock Generator OSTC - Oscillation stabilization timer status register The 8-bit OSTC register indicates the status of the main oscillator. Access This register is read-only. Address FFFF F6C2 Initial Value . The register is initialized by any reset. MSTS Table 4-6 OSTC register contents...
Page 171 Clock Generator Chapter 4 OSTS - Oscillation stabilization time select register The 8-bit OSTS register specifies the oscillation stabilization time following reset release or release of the STOP mode. The oscillation stabilization time and setup time are required when the STOP mode and IDLE mode are released, respectively.
Page 172 Chapter 4 Clock Generator For minimum oscillation stabilization / setup times refer to the Electrical Target Specification. Note When IDLE2 mode is released, set the stabilization time to the following requirements: – In case of PLL mode: PLL lockup time requirements –...
Page 173 Clock Generator Chapter 4 PCC - Processor clock control register The 8-bit PCC register controls the CPU system clock f VBCLK Access This register can be read/written in 1-bit and 8-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “CPU System Functions”...
Page 174 Chapter 4 Clock Generator Table 4-8 PCC register contents (2/2) Bit position Bit name Function 3 to 0 CK[3:0] Clock selection: Clock selection Setting prohibited Subclock f or f Note: 1. Do not change the CPU clock (by using the CK[3:0] bits) while CLKOUT is being output.
Page 175 Clock Generator Chapter 4 subclock to main 1. Setting the MCK bit to "0": Enables main clock oscillation. 2. Software wait: Insert wait status via program to wait until the oscillation stabilization time of the main clock oscillator (OSTC.MSTS = 1) is elapsed. 3.
Page 176 Chapter 4 Clock Generator PCLM - Programmable clock mode register The 8-bit PCLM register specifies the setting the programmable clock output PCL. Access This register can be read/written in 1-bit or 8-bit units. Address FFFF F82F Initial Value . The register is initialized by any reset. PCLE PCK1 PCK0...
Page 177 Clock Generator Chapter 4 RCM - Internal oscillator mode register The 8-bit RCM register specifies the operation and informs about the status of the low-speed and high-speed internal oscillators. Access This register can be read/written in 1-bit or 8-bit units. Address FFFF F80C Initial Value...
Page 178: Pll Control Registers
Chapter 4 Clock Generator 4.2.2 PLL control registers The Clock Generator’s PLL registers control and reflect the operation of the PLL. LOCKR - PLL lock status register Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time).
Page 179 Clock Generator Chapter 4 PLLCTL - PLL control register The 8-bit PLLCTL register controls the PLL function. Access This register can be read or written in 8-bit or 1-bit units. Address FFFF F82C Initial Value . The register is initialized by any reset. SELPLL PLLON Table 4-12 PLLCTL register contents...
Page 180 Chapter 4 Clock Generator PLLS - PLL lockup time specification register The 8-bit PLLS register specifies the settling time of the PLL. Access This register can be read/written in 8-bit units. Address FFFF F6C1 Initial Value . The register is initialized by any reset. PLLS2 PLLS1 PLLS0...
Page 181: Stand-By Control Registers
Clock Generator Chapter 4 4.2.3 Stand-by control registers These registers control and reflect the various stand-by modes that can be entered for saving power. PSC - Power save control register The 8-bit PSC register controls the stand-by function. The STP bit of this register specifies the stand-by mode.
Page 182 Chapter 4 Clock Generator PSMR - Power save mode control register The 8-bit PSMR register is used to specify one of the power save modes. The setting becomes effective when the mode is entered by setting PSC.STP to 1. Access This register can be read/written in 1-bit or 8-bit units.
Page 183: Prescaler3 Control Registers
Clock Generator Chapter 4 4.2.4 Prescaler3 control registers These registers control the Prescaler3 that generates f which can be applied to the Watch Timer and the Clocked Serial Interface CSIB0. Prescaler3 includes a clock divider, a counter, and a comparator. For details see “Operation of Prescaler3”...
Page 184: Clock Monitor Control Registers
Chapter 4 Clock Generator Note Do not rewrite the PRSCM0 register during Watch Timer operation. Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used to obtain an f frequency of 32,768 KHz. For details and a calculation example, please refer to “Operation of Prescaler3” on page 216.
Page 185: Selector Control Registers
Clock Generator Chapter 4 4.2.6 Selector control registers These registers are used to select the clocks and functions of timers TAAn, TMM0 and serial interfaces UARTDn, CANn. Note In this section, only the bits that refer to clock generation and distribution are described.
Page 186 Chapter 4 Clock Generator SELCNT2 - Selector control register 2 The 8-bit SELCNT2 register is used to specify the clock for UARTD0, UARTD1, CAN0 and TAAn. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F30C Initial Value .
Page 187 Clock Generator Chapter 4 SELCNT3 - Selector control register 3 The 8-bit SELCNT3 register is used to specify the clocks for UARTD2. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F30E Initial Value . The register is initialized by any reset. •...
Page 188: Option Bytes
Chapter 4 Clock Generator 4.3 Option Bytes The code flash memory versions in this product series have an option data area where a block subject to mask options is specified. When writing a program to a code flash memory version, be sure to set the option data area corresponding to the following option bytes.
Page 189: Option Byte 0000 007A H
Clock Generator Chapter 4 4.3.1 Option byte 0000 007A Address 0000 007A STOPXTAL STOPRCZ WDTMD1 RMOPIN Note Bits marked with “0” must not be changed from their value “0”. Table 4-21 Setting of option byte 0000 007A Bit position Bit name Function 7 to 6 STOPXTAL,...
Page 190: Option Byte 0000 007B H
Chapter 4 Clock Generator 4.3.2 Option byte 0000 007B Address 0000 007B SUBCLK LATENCY PLLO PRSI PLLI1 PLLI0 Note Bits marked with “0” must not be changed from their value “0”. Table 4-22 Setting of option byte 0000 007B Bit position Bit name Function SUBCLK...
Page 191: Clock Generator Operation
Clock Generator Chapter 4 4.4 Clock Generator Operation This chapter describes the specific features of the Clock Generator. For details see: • “Overview of clock operation control settings” on page 191 • “Operation state transitions” on page 192 • “Power save modes description” on page 196 •...
Page 192: Operation State Transitions
Chapter 4 Clock Generator 4.4.2 Operation state transitions The following figure illustrates the various state transitions. RESET 8 MHz internal Each STBY oscillator operation (HALT/IDLE1/IDLE2/ Software STOP) Oscillation stabilization wait Each STBY (HALT/IDLE1/IDLE2/ Software STOP) X1 main clock-through PLL operation (PLL = ON) Note 1 (PLL = ON)
Page 193 Clock Generator Chapter 4 Status transition from PLL operation Note 2 PLL operation (PLL = ON) Note 1 HALT mode Software STOP mode X1 = ON, PLL = ON X1 = OFF, PLL = OFF IDLE1 mode IDLE2 mode X1 = ON, PLL = ON X1 = ON, PLL = OFF Figure 4-3 Stand-by transition from PLL operation (PLL = ON)
Page 194 Chapter 4 Clock Generator Status transition from main clock-through operation (with PLL off) Note 2 X1 main clock-through mode (PLL = OFF) Note 1 HALT mode Software STOP mode X1 = ON, PLL = OFF X1 = OFF, PLL = OFF IDLE1 mode IDLE2 mode X1 = ON, PLL = OFF...
Page 195 Clock Generator Chapter 4 Status transition to / from subclock operation Normal operation mode (main clock operation) Subclock Main clock operation operation setting setting Subclock operation mode IDLE mode Interrupt setting Sub-IDLE mode Figure 4-6 Status transition diagram (during subclock operation) User’s Manual U18743EE1V2UM00...
Page 196: Power Save Modes Description
Chapter 4 Clock Generator 4.4.3 Power save modes description This section explains the various power save modes in detail. Table 4-24 Stand-by modes Mode Functional Outline HALT mode Mode in which only the operating clock of the CPU is stopped IDLE1 mode Mode in which all the internal operations of the chip except the oscillator, PLL and flash memory are stopped...
Page 197 Clock Generator Chapter 4 • Maskable interrupts – any unmasked maskable interrupt Note that not all these signals are available in all power save modes. Note In the following tables the clock status “operates” does not necessarily mean that the functions that use this clock source are operating as well. HALT mode In this mode, the clock oscillators continue operating, but clock supply to the CPU is stopped.
Page 198 Chapter 4 Clock Generator Table 4-25 Controller status in HALT mode (2/2) Working condition Without Subclock With Subclock CAN Controller(CAN0) Operable Interrupt Controller Operable Key interrupting function Operable Clock Monitor Operable Power-On-Clear circuit Operable Low-Voltage Detector Operable Voltage Regulator Operation continues Internal data The CPU registers, states, data and all other internal data such as the contents of the internal RAM are retained as they were before HALT mode was set...
Page 199 Clock Generator Chapter 4 IDLE1 mode In the IDLE1 mode, the main oscillator, PLL and flash memory continue operating, but clock supply to the CPU and the other on-chip peripheral functions is stopped. As a result, program execution is stopped, and the contents of the internal RAM before the IDLE1 mode was set are retained.
Page 200 Chapter 4 Clock Generator Table 4-27 Controller status in IDLE1 mode (2/2) Working condition Without Subclock With Subclock Power-On-Clear circuit Operable Low-Voltage Detector Operable Voltage Regulator Operation continues Internal data The CPU registers, states, data and all other internal data such as the contents of the internal RAM are retained as they were before IDLE1 mode was set Only when setting the ISELxx bit =1 (f ), the count operation by f...
Page 201 Clock Generator Chapter 4 (a) Release by non-maskable interrupt request or unmasked maskable interrupt request The IDLE1 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the IDLE1 mode is set in an interrupt routine, however, the operation is performed as follows: •...
Page 202 Chapter 4 Clock Generator IDLE2 mode status The following table shows the operation status in the IDLE2 mode. Table 4-29 Controller status in IDLE2 mode Working condition Without Subclock With Subclock MainOSC (f Oscillation enabled SubOSC (f Oscillation enabled 240 KHz internal oscillator (f ) Oscillation enabled 8 MHz internal oscillator (f Oscillation enabled...
Page 203 Clock Generator Chapter 4 (a) Release by non-maskable interrupt request or unmasked maskable interrupt request The IDLE2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the IDLE2 mode is set in an interrupt routine, however, the operation is performed as follows: •...
Page 204 Chapter 4 Clock Generator Oscillation waveform Main clock IDLE mode status Interrupt request ROM circuit stops. Counting of setup time Figure 4-7 IDLE2 mode timing STOP mode In the STOP mode, the subclock oscillator continues operating, but the main clock oscillator stops operating. Moreover, clock supply to the CPU and the other on-chip peripheral functions is stopped.
Page 205 Clock Generator Chapter 4 Table 4-31 Controller status in STOP mode (2/2) Working condition Without Subclock With Subclock Timer/counter TAA0 -TAA4 Stops operation TMM0 Operable if fBRG (clock of dividing Operable if f /8, INTWT or f frequency of Prescaler3) is selected as selected as count clock.
Page 206 Chapter 4 Clock Generator The STOP mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the STOP mode is set in an interrupt routine, however, the operation is performed as follows: •...
Page 207 Clock Generator Chapter 4 (c) Releasing by RESET input The operation is the same as the normal reset operation. Subclock operation mode When the subclock operation mode is set, the CPU system clock f VBCLK changed from the main system clock to the subclock. Subclock can be f .
Page 208 Chapter 4 Clock Generator Table 4-33 Controller status in subclock mode (2/2) Working condition With MainOSC operating With MainOSC stopped Serial Interface UARTD0-2 Operable UARTD0: Operable if ASCKD0 is selected input clock UARTD1-2: Operation stops CSIB0-1 Operable Operable if SCKBn input clock is selected as operation clock.
Page 209 Clock Generator Chapter 4 the other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can operate on the subclock continue operating. The sub-IDLE mode can reduce current consumption more than the subclock operation mode because the operations of the CPU, flash memory, and other on-chip peripheral functions are stopped.
Page 210 Chapter 4 Clock Generator Leaving sub-IDLE The sub-IDLE mode is released by a non-maskable interrupt request signal mode (NMI pin input or INTWDT2 signal), unmasked external interrupt request signal, unmasked internal interrupt request of a peripheral function that can operate in the sub-IDLE mode, or reset signal. The PLL returns to the operation status before the sub-IDLE mode was set.
Page 211: Available Clocks In Power Save Modes
Clock Generator Chapter 4 4.4.4 Available clocks in power save modes The following table gives an overview of the clock signals available in the various stand-by modes. Table 4-36 Clock operation in power save modes PLLI Operation status VBCLK Note2 Note2 Note2 Note2...
Page 212 Chapter 4 Clock Generator O: Operating x: Stopped Enable: Operation enable (by control register and option bytes setting) Note The working conditions are the following: - 8 MHz internal oscillator: 8 MHz internal oscillator clock operation - MainOSC: MainOSC clock operation - PLL: PLL clock operation - SubOSC:...
Page 213: Power Save Mode Activation
Clock Generator Chapter 4 4.4.5 Power save mode activation In the following procedures are described how to securely entering a power save mode. HALT mode For entering the HALT mode proceed as follows: 1. Mask all interrupts which shall not have wake-up capability by xxIC.xxMK = 0 and discard all possibly pending interrupts by xxIC.xxIF = 0.
Page 214 Chapter 4 Clock Generator In this example, maskable interrupts are permitted to leave the power save mode. // xxIC.xxMK = 0 // mask all none wake-up interrupts // xxIC.xxMK = 1 // unmask all wake-up interrupts 0x02,r10 st.b 10,PSMR[r0] // PSMR.PSM[1:0] = 10B: IDLE2 mode 0x62,r10 st.b r10,PRCMD[r0]...
Page 215: Controlling The Pll
Clock Generator Chapter 4 4.4.6 Controlling the PLL Using the PLL After the RESET signal has been released, the PLL has to be started by PLLCTL.PLLON = 1, after the main oscillator has stabilized (OSTC.MSTS = 1). Since the default mode is the clock-through mode (PLLCTL.SELPLL = 0), select the PLL mode (PLLCTL.SELPLL = 1).
Page 216: Operation Of Prescaler3
Chapter 4 Clock Generator 4.4.9 Operation of Prescaler3 Prescaler3 generates the clock f by dividing the main oscillator output signal f Description Prescaler3 consists of a clock divider, a counter, and a comparator. Figure 4-9 Prescaler3 Block Diagram Calculation The relation between the main oscillator clock (f ), prescaler clock divider selection PRSM0.BGCS0[1:2], PRSCM0 compare register value, and output clock f...
Page 217: Operation Of The Clock Monitor
Clock Generator Chapter 4 4.4.10 Operation of the Clock Monitor The Clock Monitor samples the main clock by using the on-chip 240 KHz internal oscillator. It generates a reset request signal when the oscillation of the main clock has stopped. Description The functional block diagram is shown below.
Page 218 Chapter 4 Clock Generator Start and stop The Clock Monitor operation must be enabled by setting bit CLM.CLME to 1. Once this bit has been set, it cannot be cleared to 0 by any means other than reset. The Clock Monitor is automatically started as soon as the main oscillator is stable, indicated by OSTC.MSTS = 1.
Page 219 Clock Generator Chapter 4 Normal operation Software STOP Oscillation stabilization time Normal operation operation Main clock Oscillation stabilization time Oscillation stops (set by OSTS register) Internal oscillator clock CLME Clock monitor status During Monitor stops During monitor monitor Figure 4-12 Operation in STOP mode or after STOP mode is released Operation when main clock is stopped During subclock operation (CLS bit of the PCC register = 1) or when the main...
Page 220 Chapter 4 Clock Generator Operation during and after power save modes Main oscillator If the main oscillator is stopped, the Clock Monitor changes to stand-by. When stopped the main oscillator is restarted after power save mode release, the Clock Monitor restarts automatically. Internal oscillator When the 240 KHz internal oscillator is stopped, the Clock Monitor’s operation stopped...
Page 221: Chapter 5 Interrupt Controller (Intc)
Chapter 5 Interrupt Controller (INTC) This controller is provided with a dedicated Interrupt Controller (INTC) for interrupt servicing and can process a large amount of maskable and two non- maskable interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 222 Chapter 5 Interrupt Controller (INTC) Note Default priority: The priority order when two or more maskable Interrupt/Exception Source Default Exception Handler Restored Type Control Generating Priority Code Address Name Generating Source Register Unit Reset RESET – Reset input by internal source RESET –...
Page 223 Interrupt Controller (INTC) Chapter 5 Interrupt/Exception Source Default Exception Handler Restored Type Control Generating Priority Code Address Name Generating Source Register Unit Maskable INTCB1R CB1RIC CSIB1 reception completion / CSIB1 0290H 00000290H nextPC reception error INTCB1T CB1TIC CSIB1 consecutive transmission CSIB1 02A0H 000002A0H...
Page 224: Non-Maskable Interrupts
Chapter 5 Interrupt Controller (INTC) 5.2 Non-Maskable Interrupts A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. Non-maskable interrupts of this microcontroller are available for the following requests: • NMI: NMI pin input •...
Page 225 Interrupt Controller (INTC) Chapter 5 NMI and INTWDT2 requests generated simultaneously Main routine INTWDT2 servicing NMI and INTWDT2 requests System reset (generated simultaneously) Figure 5-1 Example of non-maskable interrupt request acknowledgement operation: multiple NMI requests generated at the same time User’s Manual U18743EE1V2UM00...
Page 226 Chapter 5 Interrupt Controller (INTC) NMI being NMI request generated during NMI servicing serviced INTWDT2 NMI request generated during INTWDT2 request generated NMI servicing during NMI servicing (NP = 1 retained before NMI1 request) Main routine Main routine NMI servicing NMI servicing INTWDT2 request (Held pending)
Page 227: Operation
Interrupt Controller (INTC) Chapter 5 5.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: 1. Saves the restored PC to FEPC. 2. Saves the current PSW to FEPSW. 3.
Page 228: Restore
Chapter 5 Interrupt Controller (INTC) 5.2.2 Restore Execution is restored from the non-maskable interrupt (NMI) processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. 1.
Page 229: Non-Maskable Interrupt Status Flag (Np)
Interrupt Controller (INTC) Chapter 5 INTWDT2 Restoring by RETI instruction is not possible. Perform a system reset after interrupt servicing. 5.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execution. This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 230: Maskable Interrupts
Chapter 5 Interrupt Controller (INTC) 5.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. This microcontroller has up to 52 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 231 Interrupt Controller (INTC) Chapter 5 INT input INTC accepted xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with the same priority? Maskable interrupt request Interrupt request pending...
Page 232: Restore
Chapter 5 Interrupt Controller (INTC) 5.3.2 Restore Recovery from maskable interrupt processing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. 1.
Page 233: Priorities Of Maskable Interrupts
Interrupt Controller (INTC) Chapter 5 5.3.3 Priorities of maskable interrupts This microcontroller provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 234 Chapter 5 Interrupt Controller (INTC) Main routine Processing of a Processing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the (level 3) (level 2) priority of b is higher than that of a and interrupts are enabled.
Page 235 Interrupt Controller (INTC) Chapter 5 Note <a> to <u> in the figure are the temporary names of interrupt requests shown for the sake of explanation. The default priority in the figure indicates the relative priority between two interrupt requests. Main routine Processing of i Processing of k Interrupt...
Page 236 Chapter 5 Interrupt Controller (INTC) Caution The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Note Lower default priority Higher default priority Main routine...
Page 237: Xxicn - Maskable Interrupt Control Registers
Interrupt Controller (INTC) Chapter 5 5.3.4 xxICn - Maskable interrupt control registers An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. Access This register can be read/written in 1-bit or 8-bit units. Address FFFF F110 to FFFF F194...
Page 238 Chapter 5 Interrupt Controller (INTC) V850ES/FE3-L/ Address Register V850ES/FG3-L V850ES/FF3-L √ √ FFFFF110H LVILIC √ √ FFFFF112H LVIHIC √ √ FFFFF114H PIC0 √ √ FFFFF116H PIC1 √ √ FFFFF118H PIC2 √ √ FFFFF11AH PIC3 √ √ FFFFF11CH PIC4 √ √ FFFFF11EH PIC5 √...
Page 239 Interrupt Controller (INTC) Chapter 5 V850ES/FE3-L/ Address Register V850ES/FG3-L V850ES/FF3-L √ √ FFFFF176H KRIC √ √ FFFFF178H WTIIC √ √ FFFFF17AH WTIC FFFFF17EH FLIC – – √ FFFFF180H PIC8 – √ FFFFF182H PIC9 – √ FFFFF184H PIC10 – √ FFFFF190H UD2SIC –...
Page 240: Imrm - Interrupt Mask Registers
Chapter 5 Interrupt Controller (INTC) 5.3.5 IMRm - Interrupt mask registers These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMRm registers is equivalent to the xxMKn bit of the xxICn register. • 16 bit IMRm registers are accessible through –...
Page 241 Interrupt Controller (INTC) Chapter 5 IMR2 - Interrupt mask register 2 Address Initial value IMR2 C0TRXMK C0RECMK C0WUPMK C0ERRMK ADMK IIC0MK UD1TMK FFFFF104H FFFFH UD1RMK UD1SMK UD0TMK UD0RMK UD0SMK CB1TMK CB1RMK CB0TMK IMR3 - Interrupt mask register 3 • V850ES/FE3-L •...
Page 242: Ispr - In-Service Priority Register
Chapter 5 Interrupt Controller (INTC) 5.3.6 ISPR - In-service priority register This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 243: Maskable Interrupt Status Flag (Id)
Interrupt Controller (INTC) Chapter 5 5.3.7 Maskable interrupt status flag (ID) The ID flag is bit 5 of the PSW and this controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt requests. Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP 00000020H Bit position...
Page 244: External Interrupts Edge Detection Configuration
Chapter 5 Interrupt Controller (INTC) 5.4 External Interrupts Edge Detection Configuration The microcontroller provides the maskable external interrupts INTPn and one non-maskable interrupt (NMI). INTPn and NMI can be configured to generate interrupts upon rising, falling or both edges. Two register sets are provided to specify edges and levels for each external interrupt.
Page 245 Interrupt Controller (INTC) Chapter 5 INTR1/INTF1 - External interrupt edge specification register 1 • V850ES/FG3-L Initial Address value INTR1 INTR11 INTR10 FFFF FC22H 00H INTP10 INTP9 Initial Address value INTF1 INTF11 INTF10 FFFF FC02H 00H INTP10 INTP9 INTR3/INTF3 - External interrupt edge specification register 3 •...
Page 246 Chapter 5 Interrupt Controller (INTC) Both bytes of this 16-bit register can also be accessed bytewise with – INTF3L = INTF3[7:0] under the address FFFF FC06H – INTF3H = INTF3[15:8] under the address FFFF FC07H User’s Manual U18743EE1V2UM00...
Page 247: Software Exception
Interrupt Controller (INTC) Chapter 5 5.5 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 5.5.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: 1.
Page 248: Restore
Chapter 5 Interrupt Controller (INTC) 5.5.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. 1. Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1.
Page 249: Exception Status Flag (Ep)
Interrupt Controller (INTC) Chapter 5 5.5.3 Exception status flag (EP) The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP 00000020H Bit position...
Page 250 Chapter 5 Interrupt Controller (INTC) Exception trap (ILGOP) occurs DBPC restored PC DBPSW PSW.NP PSW.EP CPU processing PSW.ID 00000060H Exception processing Figure 5-12 Exception trap processing Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 251: Debug Trap
Interrupt Controller (INTC) Chapter 5 5.6.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. Operation When the debug trap is generated, the CPU performs the following processing, transfers control to the debug monitor routine, and shifts to debug mode.
Page 252: Multiple Interrupt Processing Control
Chapter 5 Interrupt Controller (INTC) Figure 5-15 illustrates the restore processing from a debug trap. DBRET instruction DBPC DBPSW Jump to address of restored PC Figure 5-15 Restore processing from debug trap 5.7 Multiple Interrupt Processing Control Multiple interrupt processing control is a process by which an interrupt request that is currently being processed can be interrupted during processing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is received and processed first.
Page 253 Interrupt Controller (INTC) Chapter 5 Acknowledgment of maskable interrupts in service program Service program of maskable interrupt or exception •EIPC saved to memory or register •EIPSW saved to memory or register •EI instruction (interrupt acknowledgment enabled) ¨ Maskable interrupt acknowledgment •DI instruction (interrupt acknowledgment disabled) •Saved value restored to EIPSW •Saved value restored to EIPC...
Page 254: Interrupt Response Time
Chapter 5 Interrupt Controller (INTC) Interrupt processing that has been suspended as a result of multiple processing control is resumed after the processing of the higher priority interrupt has been completed and the RETI instruction has been executed. A pending interrupt request is acknowledged after the current interrupt processing has been completed and the RETI instruction has been executed.
Page 255: Periods In Which Interrupts Are Not Acknowledged
Interrupt Controller (INTC) Chapter 5 Interrupt response time (internal system clocks) Condition Internal interrupt External interrupt Minimum 4 + analog delay time The following cases are exceptions: • In IDLE/software STOP mode 6 + analog delay time • External bit access 6 (in case of latency = 2) (in case of latency = 2) Maximum...
Page 256 Chapter 5 Interrupt Controller (INTC) User’s Manual U18743EE1V2UM00...
Page 257: Chapter 6 Key Interrupt Function
Chapter 6 Key Interrupt Function 6.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the key return mode register (KRM). Table 6-1 Assignment of Key Return Detection Pins Flag Pin Description...
Page 258: Control Register
Chapter 6 Key Interrupt Function 6.2 Control Register KRM - Key return mode register The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F300 Initial Value...
Page 259: Chapter 7 Flash Memory
Chapter 7 Flash Memory The following V850ES/Fx3-L devices are equipped with internal flash memory Product Device Code flash size V850ES/FE3-L µPD70F3610 64 KB µPD70F3611 96 KB µPD70F3612 128 KB µPD70F3613 192 KB µPD70F3614 256 KB V850ES/FF3-L µPD70F3615 64 KB µPD70F3616 96 KB µPD70F3617 128 KB...
Page 260: Code Flash Memory Overview
Chapter 7 Flash Memory 7.1 Code Flash Memory Overview 7.1.1 Code flash memory features • 4-byte/1 CPU clock access during instruction fetch • All-blocks or multiple blocks batch erase or single block erase • Erase/write with single power supply • Communication with dedicated flash programmer via various serial interfaces •...
Page 261: Code Flash Memory Mapping
Flash Memory Chapter 7 7.1.2 Code flash memory mapping The microcontroller’s internal code flash memory area is divided into blocks of 2 KB respectively 4 KB blocks and can be programmed/erased in block units. All or some of the blocks can also be erased at once. Following figures list the block structures and address assignments for all V850ES/Fx3-L devices with code flash memory.
Page 262: Code Flash Memory Functional Outline
Chapter 7 Flash Memory 7.1.3 Code flash memory functional outline Serial programming The internal flash memory of the microcontroller can be rewritten by using the rewrite function of a dedicated flash programmer, regardless of whether the microcontroller has already been mounted on the target system or the device is not mounted (off-board/on-board programming).
Page 263 Flash Memory Chapter 7 Table 7-1 Flash memory write methods Environment Interface Outline Operation Mode Serial Serial I/F (UART, Flash memory programming is done by an external Flash memory programming CSI) flash programmer. programming The device may be mounted on the target system (on- mode board) or unmounted (off-board) by using a suitable programming adapter board.
Page 264 Chapter 7 Flash Memory Table 7-2 Basic functions for flash memory modifications Support (√: Supported, ×: Not supported) Function Functional outline Serial Self-programming programming √ √ Block erasure The contents of specified memory blocks are erased. Multiple block The contents of the specified successive multiple √...
Page 265: Code Flash Memory Erasure And Rewrite
Flash Memory Chapter 7 The boot block cluster protection flag is not erased. 7.1.4 Code flash memory erasure and rewrite Erasure According to its block structure the flash memory can be erased in two different modes. • All-blocks batch erasure (chip erase) All blocks are erased all together.
Page 266: Flash Programming With Flash Programmer
Chapter 7 Flash Memory 7.2 Flash Programming with Flash Programmer A dedicated flash programmer can be used for external writing of the flash memory. • On-board programming The contents of the flash memory can be rewritten with the microcontroller mounted on the target system. Mount a connector that connects the flash programmer on the target system.
Page 267: Communication Mode
Flash Memory Chapter 7 7.2.2 Communication mode The communication between the flash programmer and the microcontroller utilizes the asynchronous serial interface UART or optionally the synchronous serial interface CSI. For programming via the synchronous serial interface CSI without handshake and with handshake modes are supported. In the latter mode the port pin HSPORT is used for the programmer’s handshake signal HS.
Page 268 Chapter 7 Flash Memory CSI with handshake (CSI + HS) The external flash programmer offers various choices of available clock rates. FLMD0 (FLMD1 Note FLMD0 (FLMD1 Note Axxxx Bxxxxx RESET RESET Cxxxxxx STATVE PG-FP4 flash programmer V850 microcontroller HSPORT Note: FLMD1 connection may be replaced by a pull-down resistor on the board Figure 7-5 Communication with flash programmer via CSI with handshake The flash programmer outputs a transfer clock and the microcontroller...
Page 269: Pin Connection With Flash Programmer Pg-Fp4
Flash Memory Chapter 7 7.2.3 Pin connection with flash programmer PG-FP4 A connector must be mounted on the target system to connect the flash programmer for on-board writing. In addition, functions to switch between the normal operation mode and flash memory programming mode and to control the microcontroller’s reset pin must be provided on the board.
Page 270 Chapter 7 Flash Memory Table 7-5 Wiring of V850ES/Fx3-L flash writing adapters for CSIB Flash programmer (FG-FP4) UARTA0 CSIB0 + HS CSIB0 N-Wire Name of connection pin FA board Signal Pin function Pin name Pin name Pin name Pin name name SI/RxD Receive signal...
Page 271: Flash Memory Programming Control
Flash Memory Chapter 7 7.2.4 Flash memory programming control The procedure to program the flash memory is illustrated below. Reset/FLMD0 pulse supply Note: A reset pulse is required to initiate the selection of the flash programming mode. Figure 7-7 Flash memory programming procedure User’s Manual U18743EE1V2UM00...
Page 272 Chapter 7 Flash Memory Operation mode control To rewrite the contents of the flash memory by using the flash programmer, set the microcontroller in the flash memory programming mode. To set this mode, set the FLMD0 and FLMD1 pins as shown in Table 7-7 on page 272 and release RESET.
Page 273 Flash Memory Chapter 7 Potential conflicts with on-board signal connections Serial I/O signals If other devices are connected to the serial interface pins in use for flash memory programming in on-board programming mode take care that the concerned signals do not conflict with the signals of the flash programmer and the microcontroller.
Page 274 Chapter 7 Flash Memory Ports The V850 port pins adopts following status during serial programming: Ports used for programming are configured as UART respectively CSI pins. All other pins remain in their default state after reset release. In case the default state after reset of the pins not used for programming is inport port or high -impedance output port, pay attention to other devices connected to these pins.
Page 275 Flash Memory Chapter 7 Selection of the communication mode The communication interface is chosen by applying a specified number of pulses to the FLMD0 pin after reset release. Note that this is handled by the flash programmer. Figure 7-11 on page 275 gives an example how the UART is established for the communication between the flash programmer and the microcontroller.
Page 276 Chapter 7 Flash Memory Communication commands The flash programmer sends commands to the microcontroller. Depending on the commands, the microcontroller returns status information or the requested data. Command Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 Status Data Flash programmer V850 microcontroller Figure 7-12 Communication commands exchange The following table lists the flash memory control commands of the microcontroller.
Page 277: Code Flash Self-Programming
By using this flash macro service and a self-programming library, provided by NEC, the user’s program is able to rewrite the flash memory with data, transferred in advance to the internal RAM.
Page 278: Self-Programming Enable
Chapter 7 Flash Memory 7.3.1 Self-programming enable The self-programming functions can be started out of the normal user mode of the microcontroller. The microcontroller must be set into self-programming mode via the self- programming library. For security reasons writing and erasing of the flash memory must be additionally permitted by setting the external FLMD0 pin to high level.
Page 279: Secure Self-Programming (Boot Cluster Swapping)
Flash Memory Chapter 7 7.3.3 Secure self-programming (boot cluster swapping) The V850 flash microcontrollers support a mechanism to swap a cluster of code flash memory blocks, starting from address 0000 0000 , with another cluster of the same size, located immediately above the first one. Caution Boot cluster swapping is only supported, if the variable reset vector remains in its default state 0000 0000...
Page 280 Chapter 7 Flash Memory Secure self- The boot cluster swapping function enables secure self-programming. In case programming the boot code shall be rewritten, the new code can be written to the inactive boot block cluster, while the boot_flag remains in its previous state. If rewriting of the boot block cluster has been completed successfully, the boot_flag can be inverted, making the new boot code active.
Page 281 Flash Memory Chapter 7 Table 7-10 Relation between boot block and boot swap cluster Devices with 2 KB blocks ≤ 256 KB code flash) Number of boot blocks Boot swap Boot block cluster cluster 0000 0000H - 0000 07FFH 0000 0000H (2 KB) 0000 1FFFH RESV - 0000 0FFFH...
Page 282 Chapter 7 Flash Memory Figure 7-16 on page 282 illustrates an example with following settings: • number of boot blocks: 2 (boot block cluster contains 2 blocks), thus the active boot block cluster comprises – if boot_flag: blocks 0and 1 –...
Page 283: Interrupt Handling During Flash Self-Programming
Flash Memory Chapter 7 7.3.4 Interrupt handling during flash self-programming This microcontroller provides functions to maintain interrupt servicing during the self-programming procedure. Since neither the interrupt vector table nor the interrupt handler routines, which are normally located in the flash memory, are accessible while self- programming is active, interrupt acknowledges have to be re-routed to non- flash memory, i.e.
Page 284: Variable Reset Vector
Chapter 7 Flash Memory 7.4 Variable Reset Vector This microcontroller provides a facility to specify the address of the first user software instruction to be executed after reset release. By default the first user’s instruction to be executed after reset, i.e. the reset vector, is the one stored at address 0000 0000 .
Page 285: Flash Mask Options
Flash Memory Chapter 7 7.5 Flash Mask Options In the option data area, a block subject to mask options is specified. Make sure to set the option data area corresponding to the following option bytes in the program at address 007A /007B as default data.
Page 286 Chapter 7 Flash Memory Address Set Value Setting 007A Internal oscil- Can be stopped. lator: WDT2: Count clock can be selected. Overflow signal can be selected from INTWDT2 or WDT2RES. Sub oscilla- Crystal resonator connection tor: Internal oscil- Cannot be stopped. lator: WDT2: Count clock can be selected.
Page 287 Flash Memory Chapter 7 0000 007B SUBCLK PLLO PRSI PLLI1 PLLI0 PLLI1 PLLI0 Selection of PLL input clock to PLL PLLI = fx/2 PLLI = fx/4 PLLI PRSI Peripheral clock selection XP1, XP1, PLLO PLL output clock selection Setting prohibited PLLO SUBCLK Clock source at sublock operating mode...
Page 288: Prdselh Register - Product Selection Code Register High
Chapter 7 Flash Memory 7.5.1 PRDSELH register - Product selection code register High The 16-bit PRDSELH register specifies the RAM start address of the device. Access The register can be accessed in 16-bit units. Address FFFFFCCA Initial Value Device depending (for details see table below) PRDSELH RAM3...
Page 289: Chapter 8 Data Protection And Security
Chapter 8 Data Protection and Security 8.1 Overview The microcontroller supports various methods for securing safe (re-)programming of the internal flash memory and protecting of the flash memory data against undesired access, such as illegal read-out or illegal reprogramming. Security functions Security functions provide countermeasures against unexpected failures during reprogramming processes.
Page 290 Chapter 8 Data Protection and Security You can specify your own 10-byte ID code and program it to the internal flash memory by an external flash writer or with the self-programming feature. The ID code is located in the address range 0000 0070 to 0000 0079 The protection levels are summarized in Table 8-1 Table 8-1...
Page 291: Flash Programmer And Self-Programming Protection
Data Protection and Security Chapter 8 8.3 Flash Programmer and Self-Programming Protection In general, illegal read-out and re-programming of the flash memory contents is possible via the flash writer interface and the self-programming feature.The available flash memory protection methods are as follows. Serial programming It is possible to prohibit any access from external via the serial programming interface,e.g.
Page 292 Chapter 8 Data Protection and Security Read-out protection flag Set this flag to disable the feature that allows reading back the flash memory via external flash programmer interfaces. No flash content can be read out. This flag does not affect the self-programming interface. In self-programming mode read-out of flash memory content is further on possible.
Page 293 Data Protection and Security Chapter 8 Table 8-3 Rewriting operation when erasing/writing is enabled/prohibited Block erasure Write Chip None None Prohibition state Programming mode Boot Boot erasure boot boot area area area area Rewriting All enabled Self-programming – boot area Serial programming enabled Block erase...
Page 294 Chapter 8 Data Protection and Security User’s Manual U18743EE1V2UM00...
Page 295: Chapter 9 Bus Control Unit (Bcu)
Figure 9-1 Bus and Memory Control block diagram Busses The busses are abbreviated as follows: • NPB: NEC peripheral bus • VSB: V850 system bus • VDB: V850 data bus • VFB: V850 fetch bus The Bus Control Unit (BCU) controls the access to the on-chip peripherals.
Page 296: Peripheral I/O Area
Chapter 9 Bus Control Unit (BCU) 9.1.1 Peripheral I/O area Two areas of the address range are reserved for the registers of the on-chip peripheral functions. These areas are called “peripheral I/O areas”: Table 9-1 Peripheral I/O areas Name Address range Size Fixed peripheral I/O area 03FF F000...
Page 297 The PPA extends the fixed peripheral I/O area and assigns an additional 12 KB address space for accessing on-chip peripherals. The figure below illustrates the programmable peripheral I/O area (PPA). 03FF FFFFH Peripheral I/O register NPB (NEC Peripheral Bus) (4 KB) 03FF F000H same area 03FE EFFFH Programmable...
Page 298: Npb Access Timing
Chapter 9 Bus Control Unit (BCU) 9.1.2 NPB access timing All accesses to the peripheral I/O areas are passed over to the NPB bus via the VSB - NPB bus bridge BBR. Read and write access times to registers via the NPB depend on the register (refer to “Registers Access Times”...
Page 299: Bus Properties
Bus Control Unit (BCU) Chapter 9 9.1.3 Bus properties This section summarizes the properties of the internal bus. Bus access The number of CPU clocks necessary for accessing each resource is as follows: Table 9-2 number of bus access clocks Internal ROM (32 bits) Internal RAM...
Page 300 Chapter 9 Bus Control Unit (BCU) Data space The microcontroller device is provided with an address misalign function. By this function, data of any format (word: 32 bit, halfword: 16 bit, byte: 8 bit) can be placed to any address in memory, even though the address is not aligned to the data format (that means address 4n for words, address 2n for halfwords).
Page 301: Registers
Bus Control Unit (BCU) Chapter 9 9.2 Registers Access to the on-chip peripherals is controlled and operated by registers of the Bus Control Unit (BCU): Table 9-3 Bus and memory control register overview Module Register name Shortcut Address Bus Control Unit (BCU) Peripheral area selection control register FFFF F064 Internal peripheral function wait control register...
Page 302 Chapter 9 Bus Control Unit (BCU) The base address PBA is calculated by PBA = BPC.PA[13:0] x 2 Table 9-5 shows how the addresses of the programmable peripheral area are assembled. The base address PBA is highlighted. Table 9-5 Address range of programmable peripheral area (12 KB) …...
Page 303 Bus Control Unit (BCU) Chapter 9 Table 9-6 VSWC register contents (2/2) Bit position Bit name Function Data wait for internal bus: VSWL2 VSWL1 VSWL0 Number of data wait states 1 CPU system clock (VBCLK) 2 CPU system clock (VBCLK) 2 to 0 VSWL[2:0] 3 CPU system clock (VBCLK)
Page 304 Chapter 9 Bus Control Unit (BCU) Preliminary User’s Manual U18743EE1V2UM00...
Page 305: Chapter 10 16-Bit Timer/Event Counter Aa
Chapter 10 16-Bit Timer/Event Counter AA The V850ES/Fx3-L microcontrollers have following instances of the 16-bit timer/event counter AA: V850ES/ V850ES/ V850ES/ FE3-L FF3-L FG3-L Instances Names TAA0 to TAA4 Throughout this chapter, the individual instances of Timer AA are identified by “n”, for example, TAAnCTL0 for the TAAn control register 0.
Page 306: Function Outline
Chapter 10 16-Bit Timer/Event Counter AA 10.2 Function Outline • Capture trigger input signal × 2 • External trigger input signal × 1 • Clock select × 8 • External event count input × 1 • Readable counter × 1 •...
Page 307 16-Bit Timer/Event Counter AA Chapter 10 Inter nal b us TAAnCTL0 TAAnIOC2 TAAnOPT1 TAAnCE TAAnCKS2-0 TAAnESS1-0 TAAnETS1-0 TAAnCE TAAnCSE or f /2 or f TAAnCCR0 /4 or f CCR0 b uff er TAAnCNT0 Load INTTAAnCC0 register /128 or f /256 or f Clear TAAnCE Edge...
Page 308 Chapter 10 16-Bit Timer/Event Counter AA TIAA00 TIAA10 Edge Edge TSOUT detector detector RXDD0 from CAN0 TIAA11 TIAA01 Edge Edge detector detector RXDD1 INTTM0EQ0 SELCNT0 SELCNT0 Inter nal bu s Internal bus Figure 10-2 Input circuit of TAA0 (left) and TAA1 (right) TIAA30 Edge detector...
Page 309 16-Bit Timer/Event Counter AA Chapter 10 TAAnCCR0 - TAA capture/compare register 0 The TAAnCCR0 register is a 16-bit register that operates either as capture register or as a compare register. In free-running mode, this register can be used as a capture register or as a compare register specified by bit TAAnOPT0.TAAnCCS0.
Page 310 Chapter 10 16-Bit Timer/Event Counter AA TAAnCCR1 - TAA capture/compare register 1 The TAAnCCR1 register is a 16-bit register that operates either both as a capture register or as a compare register. In free-running mode, this register can be used as a capture register or as a compare register specified by bit TAAnOPT0.TAAnCCS1.
Page 311 16-Bit Timer/Event Counter AA Chapter 10 TAAnCNT - TAA counter read buffer register TAAnCNT register is a read buffer register that can read 16-bit counter values. This register is read-only, using a 16-bit memory manipulation instruction. RESET input sets this register to 0000H. When TAAnCE bit of TAAnCTL0 equals 0, 0000H is read from this register.
Page 312: Input Selection Registers
Chapter 10 16-Bit Timer/Event Counter AA 10.4 Input Selection Registers These registers are used to select the inputs to timers. Note In this section, only the bits that refer to Timer AA input selections are described. For further information concerning the other bits please refer to “Clock Generator”...
Page 313 16-Bit Timer/Event Counter AA Chapter 10 Note If the INTTM0EQ0 interrupt signal is used for the TIAA01 input signal, use in the following range. ≥ TMM operation clock period TAA operation clock period x 4 SELCNT3 - Selector control register 3 Access This register can be read/written in 8-bit or 1-bit units.
Page 314: Control Registers
Chapter 10 16-Bit Timer/Event Counter AA 10.5 Control Registers TAAnCTL0 - TAA control register 0 TAAn control register 0 is an 8-bit register that controls the operation of timer AA. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 315 16-Bit Timer/Event Counter AA Chapter 10 Selection of internal count clock TAAnCTL0 register n = 0, 2, 4 n = 1, 3 SELCNT2.ISEL2[4:0] Input TAAn TAAn TAAn PRSI = 0 PRSI = 1 PRSI = 0 PRSI = 1 CKS2 CKS1 CKS0 /128...
Page 316 Chapter 10 16-Bit Timer/Event Counter AA TAAnCTL1 - TAA timer control register 1 TAAn control register 1 is an 8-bit register that controls the operation of timer AA. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 317 16-Bit Timer/Event Counter AA Chapter 10 TAAnMD2 TAAnMD1 TAAnMD0 Timer mode selection Interval timer mode External event counter mode External trigger pulse output mode One-shot pulse mode PWM mode Free-running mode Pulse width measurement mode Setting prohibited Caution Set bits TAAnEEE and TAAnMD2 to TAAnMD0 when TAAnCE = 0. (The same value can be written when TAAnCE = 1.) The operation is not guaranteed when rewriting is performed when TAAnCE = 1.
Page 318 Chapter 10 16-Bit Timer/Event Counter AA TAAnIOC0 - TAA dedicated I/O control register 0 The TAAnIOC0 register is an 8-bit register that controls the timer output. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H. Address: TAA0IOC0 FFFFF592H, TAA1CTL0 FFFFF5A2H, TAA2IOC0 FFFFF5B2H, TAA3IOC0 FFFFF5C2H, TAA4IOC0 FFFFF5D2H...
Page 319 16-Bit Timer/Event Counter AA Chapter 10 TAAnIOC1 - TAA dedicated I/O control register 1 The TAAnIOC1 register is an 8-bit register that controls the valid edge for the external input signals (TIAAn0 and TIAAn1). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 320 Chapter 10 16-Bit Timer/Event Counter AA Rewrite during If the edge specification for the capture operation shall be changed, while the timer operation timer remains in operation (TAAnCTL0.TAAnCE = 1), only a single bit of the edge specification bits TAAnIOC1.TAAnIS[k:i] of a dedicated capture input may be changed with a single write operation.
Page 321 16-Bit Timer/Event Counter AA Chapter 10 TAAnIOC2 - TAA I/O control register 2 The TAAnIOC2 register is an 8-bit register that controls the valid edge for external event count input signals (TIAAn0) and external trigger input signal (TIAAn0). This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 322 Chapter 10 16-Bit Timer/Event Counter AA Rewrite during If the edge specification for the external event count input and external trigger timer operation input shall be changed, while the timer remains in operation (TAAnCTL0.TAAnCE = 1), only a single bit of the edge specification bits TAAnIOC2.TAAnEES[k:i] / TAAnIOC2.TAAnETS[k:i] of a dedicated capture input may be changed with a single write operation.
Page 323 16-Bit Timer/Event Counter AA Chapter 10 TAAnIOC4 - TAA I/O control register 4 The TAAnIOC4 register is an 8-bit register that controls the output function of Timer AA. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 324 Chapter 10 16-Bit Timer/Event Counter AA TAAnOPT0 - TAA option register 0 The TAAnOPT0 register is an 8-bit register used to set the capture/compare operation and detect overflow. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 325 16-Bit Timer/Event Counter AA Chapter 10 TAAnOPT1 - TAA option register 1 The TAAnOPT1 register is an 8-bit register used to set the 32-bit capture mode by cascading two Timer AA. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 326: Operation
Chapter 10 16-Bit Timer/Event Counter AA 10.6 Operation Timer AA can perform the following operations when not in cascade mode: TAAnEST TIAAn0 TAAnEEE Capture/ Compare Operation Software External Count clock Compare Write trigger bit trigger input selection Selection Interval timer mode Invalid Invalid Internal/TIAAn0...
Page 327: Anytime Write And Reload
16-Bit Timer/Event Counter AA Chapter 10 10.6.1 Anytime write and reload TAAnCCR0 and TAAnCCR1 register rewrite is possible for timer AA during timer operation (TAAnCE = 1), but the write method (any time write, reload) differs depending on the mode. Anytime write When data is written to the TAAnCCRm register during timer operation, it is transferred at any time to CCRm buffer register and used as the 16-bit counter...
Page 328 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 16-bit counter TAAnCCR0 CCR0 buffer 0000H register TAAnCCR1 CCR1 buffer 0000H register INTTAAnCC0 INTTAAnCC1 Figure 10-5 Timing diagram for anytime write D01, D02: Setting values of TAAnCCR0 register (0000H to FFFFH) D11, D12: Setting values of TAAnCCR1 register (0000H to FFFFH) The above timing chart illustrates an example of the operation in the interval timer mode.
Page 329 16-Bit Timer/Event Counter AA Chapter 10 Reload When data is written to the TAAnCCR0 and TAAnCCR1 registers during timer operation, it is compared with the value of the 16-bit counter via the CCRm buffer register. The values of the TAAnCCR0 and TAAnCCR1 registers can be rewritten when TAAnCE = 1.
Page 330 Chapter 10 16-Bit Timer/Event Counter AA Note Above flowchart illustrates an example of the PWM mode operation. m = 0, 1 TAAnCE = 1 16-bit counter TAAnCCR0 CCR0 buff er 0000H register Note Same value write TAAnCCR1 CCR1 buff er 0000H register Note...
Page 331: Interval Timer Mode (Taanmd2 To Taanmd0 = 000 B )
16-Bit Timer/Event Counter AA Chapter 10 10.6.2 Interval timer mode (TAAnMD2 to TAAnMD0 = 000 In the interval timer mode, an interrupt request signal (INTTAAnCC0) is generated upon a match between the setting value of the TAAnCCR0 register and the value of the 16-bit counter, and the 16-bit counter is cleared. The TAAnCCR0 register can be rewritten when TAAnCE = 1, and when a value is set to TAAnCCR0 with a write instruction from the CPU, it is transferred to the CCR0 buffer register through any time write mode, and is compared with the...
Page 332 Chapter 10 16-Bit Timer/Event Counter AA Note The 16-bit counter is not cleared when its value matches the value of TAAnCCR1. TAAnCE = 1 FFFFH 16-bit Note counter TAAnCCR0 CCR0 buffer 0000H register TAAnCCR1 CCR1 buffer 0000H register INTTAAnCC0 INTTAAnCC1 TOAAn0 TOAAn1 Figure 10-9...
Page 333 16-Bit Timer/Event Counter AA Chapter 10 TAAnCE = 1 FFFFH 16-bit counter TAAnCCR0 CCR0 buffer 0000H register TAAnCCR1 CCR1 buffer 0000H register INTTAAnCC0 INTTAAnCC1 TOAAn0 TOAAn1 Figure 10-10 Basic operation timing in interval timer mode when D1 = D2; TAAnCCR0 and TAAnCCR1 are not rewritten, and TOAAn0 and TOAAn1 are output (TAAnOE0 = 1, TAAnOE1 = 1, TAAnOL0 = 0, TAAnOL1 = 1) D1: Setting value of TAAnCCR0 register (0000H to FFFFH)
Page 334 Chapter 10 16-Bit Timer/Event Counter AA When a new value is written to the TAAnCCR0 register that is smaller than the TAAn counter value at that moment, the counter will run to up to FFFFH and restart counting at 0000H. When the value of the counter then matches the TAAnCCR0 register a compare event will occur..
Page 335: External Event Counter Mode (Taanmd2 To Taanmd0 = 001 B )
16-Bit Timer/Event Counter AA Chapter 10 10.6.3 External event counter mode (TAAnMD2 to TAAnMD0 = 001 In the external event count mode, the external event count input (TIAAn0 pin input) is used as a count-up signal. Regardless of the setting of the TAAnEEE bit of the TAAnCTL0 register, 16-bit timer/event counter AA counts up the external event count input (TIAAn0 pin input) when it is set in the external event count mode.
Page 336 Chapter 10 16-Bit Timer/Event Counter AA START Initial setting • Clock selection (TAAnCTL0: TAAnCKS[2:0]) • Set external event count mode Note 1 (TAAnCTL1: TAAnMD[2:0] = 001B) • Set valid edge (TAAnIOC2: TAAnEES[1:0]) • Compare register setting (TAAnCCR0 and TAAnCCR1) (TAAnOPT0: TAAnCCS[1:0]=00) Timer operation enable (TAAnCE = 1) →...
Page 337 16-Bit Timer/Event Counter AA Chapter 10 TAAnCE = 1 FFFFH 16-bit counter TAAnCCR0 CCR0 buff er 0000H register TAAnCCR1 CCR1 buff er 0000H register INTTAAnCC0 INTTAAnCC1 TOAAn1 Figure 10-13 Basic Operation Timing in External Event Counter Mode When D1 > D2 > D3; rewrite TAAnCCR0 only; TOAAn1 is not output (TAAnOE0 = 0, TAAnOE1 = 0, TAAnOL0 = 0, TAAnOL1 = 1) D1, D2: Setting values of TAAnCCR0 register (0000H to FFFFH) D3: Setting value of TAAnCCR1 register (0000H to FFFFH)
Page 338 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH 16-bit counter TAAnCCR0 CCR0 buff er 0000H register TAAnCCR1 CCR1 buff er 0000H register INTTAAnCC0 INTTAAnCC1 TOAAn1 Figure 10-14 Basic Operation Timing in External Event Counter Mode When D1 = D2; TAAnCCR0 and TAAnCCR1 are not rewritten, TOAAn1 is output (TAAnOE0 = 1, TAAnOE1 = 1, TAAnOL0 = 0, TAAnOL1 = 1) D1: Setting value of TAAnCCR0 register (0000H to FFFFH)
Page 339: External Trigger Pulse Mode (Taanmd2 To Taanmd0 = 010 B )
16-Bit Timer/Event Counter AA Chapter 10 10.6.4 External trigger pulse mode (TAAnMD2 to TAAnMD0 = 010 When TAAnCE = 1 in the external trigger pulse mode, the 16-bit counter stops at FFFFH and waits for a trigger condition (input of an external trigger (TIAAn0 pin input) or SW trigger by setting of TAAnEST bit)).
Page 340 Chapter 10 16-Bit Timer/Event Counter AA START • Clock selection (TAAnCTL0: TAAnCKS[2:0], Initial settings TAAnCTL1: TAAnEEE=0) • External trigger pulse output mode setting Note 1 (TAAnCTL1: TAAnMD[2:0] = 010B) • Compare register setting (TAAnCCR0, TAA,CCR1) (TAAnOPT0: TAAnCCS[1:0] = 00) Timer operation enable (TAAnCE = 1) External trigger →...
Page 341 16-Bit Timer/Event Counter AA Chapter 10 TAAnCE = 1 FFFFH 16-bit Note counter External trigger (TIAAn0 pin) TAAnCCR0 CCR0 buffer 0000H register TAAnCCR1 CCR1 buffer 0000H register TOAAn1 TOAAn0 Figure 10-16 Basic Operation Timing in External Trigger Pulse Output Mode (TAAnOE0 = 1, TAAnOE1 = 1, TAAnOL0 = 0, TAAnOL1 = 0) Note The 16-bit counter is not cleared when it matches the CCR1 buffer register.
Page 342: One-Shot Pulse Mode (Taanmd2 To Taanmd0 = 011 B )
Chapter 10 16-Bit Timer/Event Counter AA 10.6.5 One-shot pulse mode (TAAnMD2 to TAAnMD0 = 011 When TAAnCE is set to 1 in the one-shot pulse mode, the 16-bit counter waits for the setting of the TAAnEST bit (to 1) or a trigger that is input when the edge of the TIAAn0 pin is detected, while holding FFFFH.
Page 343 16-Bit Timer/Event Counter AA Chapter 10 STAR T Initial settings • Clock selection (TAAnCTL1: TAAnEEE = 0) (TAAnCTL0: TAAnCKS[2:0]) • One-shot pulse mode setting (TAAnCTL1: TAAnMD[2:0]=011) • Compare register setting (TAAnCCR0, TAAnCCR1) Timer operation enable (TAAnCE = 1) → Transfer of TAAnCCR0, TAAnCCR1 values to CCR0 buffer register and CCR1 buffer register Trigger wait status, 16-bit counter in...
Page 344 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 TAAnEST = 1 FFFFH Note 16-bit counter External trigger (TIAAn0 pin) TAAnCCR0 CCR0 buffer 0000H register TAAnCCR1 CC1 buffer 0000H register INTTAAnCC0 INTTAAnCC1 TOAAn1 TOAAn0 Figure 10-18 Timing of Basic Operation in One-Shot Pulse Mode (TAAnOE0 = 1, TAAnOE1 = 1, TAAnOL0 = 0, TAAnOL1 = 0) Note The 16-bit counter starts counting up when either TAAnEST = 1 is set or the...
Page 345: Pwm Mode (Taanmd2 To Taanmd0 = 100 B )
16-Bit Timer/Event Counter AA Chapter 10 10.6.6 PWM mode (TAAnMD2 to TAAnMD0 = 100 In the PWM mode, TAAn capture/compare register 1 (TAAnCCR1) is used to set the duty factor and TAAn capture/compare register 0 (TAAnCCR0) is used to set the cycle. By using these two registers and operating the timer, variable- duty PWM is output.
Page 346 Chapter 10 16-Bit Timer/Event Counter AA START Initial setting • Select clock. (TAAnCTL0: TAAnCKS[2:0]) • Set PWM mode. (TAAnCTL1: TAAnMD[2:0] = 100B) • Set compare register. (TAAnCCR0, TAAnCCR1) Enable timer operation (TAAnCE = 1) → Transfer value of TAAnCCRm register to CCRm buffer register 16-bit counter matches TAAnCCR1.
Page 347 16-Bit Timer/Event Counter AA Chapter 10 START Initial setting • Select clock. (TAAnCTL0: TAAnCKS[2:0]) • Set PWM mode. (TAAnCTL1: TAAnMD[2:0] = 100B) • Set compare register. (TAAnCCR0, TAAnCCR1) Enable timer operation (TAAnCE = 1) → Transfer value of TAAnCCRm register to CCRm buffer register 16-bit counter matches TAAnCCR1.
Page 348 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH 16-bit counter TAAnCCR0 CCR0 buffer 0000H register TAAnCCR1 CCR1 buffer 0000H register TOAAn1 TOAAn0 Figure 10-21 Basic Operation Timing in PWM Mode When rewriting TAAnCCR1 value (TAAnOE0 = 1, TAAnOE1 = 1, TAAnOL0 = 0, TAAnOL1 = 0) D00: Set value of TAAnCCR0 register (0000H to FFFFH) D10, D11, D12, D13: Set value of TAAnCCR1 register (0000H to FFFFH) Duty of TOAAn1 output =...
Page 349 16-Bit Timer/Event Counter AA Chapter 10 TAAnCE = 1 FFFFH 16-bit counter TAAnCCR0 Note CCR0 buffer 0000H register Same value write TAAnCCR1 CCR1 buffer 0000H register TOAAn1 TOAAn0 Figure 10-22 Basic Operation Timing in PWM Mode When TAAnCCR0, TAAnCCR1 values are rewritten (TAAnOE0 = 1, TAAnOE1 = 1, TAAnOL0 = 0, TAAnOL1 = 0) Note Reload is not performed because the TAAnCCR1 register was not rewritten.
Page 350: Free-Running Mode (Taanmd2 To Taanmd0 = 101 B )
Chapter 10 16-Bit Timer/Event Counter AA 10.6.7 Free-running mode (TAAnMD2 to TAAnMD0 = 101 In the free-running mode, both the interval function and the compare function can be realized by operating the 16-bit counter as a free-running counter and selecting capture/compare operation with the TAAnCCS1 and TAAnCCS0 bits. The settings of the TAAnCCS1 and TAAnCCS0 bits of the TAAnOPT0 register are valid only in the free-running mode.
Page 351 16-Bit Timer/Event Counter AA Chapter 10 START Initial settings • Clock selection (TAAnCTL0: TAAnCKS[2:0]) Free-running mode setting • (TAAnCTL1: TAAnMD[2:0] = 101B) TAAnCCS[1:0] setting TAAnCCS[1:0] = 11 TAAnCCS[1:0] = 10 TAAnCCS[1:0] = 00 TAAnCCS[1:0] = 01 TIAAn1 edge detection Timer operation enable TIAAn0 edge detection TIAAn0, TIAAn1 edge det.
Page 352 Chapter 10 16-Bit Timer/Event Counter AA When TAAnCCS1 = 0, and TAAnCCS0 = 0 settings (interval function description, compare function) When TAAnCE = 1 is set, the 16-bit counter counts from 0000H to FFFFH and the free-running count-up operation continues until TAAnCE = 0 is set. In this mode, when a value is written to the TAAnCCR0 and TAAnCCR1 registers, they are transferred to the CCR0 buffer register and the CCR1 buffer register (any time write mode).
Page 353 16-Bit Timer/Event Counter AA Chapter 10 When TAAnCCS1 = 1 and TAAnCCS0 = 1 settings (capture function description) When TAAnCE = 1, the 16-bit counter counts from 0000H to FFFFH and free- running count-up operation continues until TAAnCE = 0 is set. During this time, values are captured by capture trigger operation and are written to the TAAnCCR0 and TAAnCCR1 registers.
Page 354 Chapter 10 16-Bit Timer/Event Counter AA When TAAnCCS1 = 1 and TAAnCCS0 = 0 When TAAnCE = 1 is set, the counter counts from 0000H to FFFFH and free- running count-up operation continues until TAAnCE = 0 is set. The TAAnCCR0 register is used as a compare register.
Page 355 16-Bit Timer/Event Counter AA Chapter 10 When TAAnCCS1 = 0 and TAAnCS0 = 1 When TAAnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH and free-running count-up operation continues until TAAnCE = 0 is set. The TAAnCCR1 register is used as a compare register.
Page 356: Pulse Width Measurement Mode (Taanmd2 To Taanmd0 = 110B)356
Chapter 10 16-Bit Timer/Event Counter AA 10.6.8 Pulse width measurement mode (TAAnMD2 to TAAnMD0 = 110B) In the pulse width measurement mode, free-running count is performed. The value of the 16-bit counter is saved to capture register 0 (TAAnCCR0), or capture register 1 (TAAnCCR1) respectively, and the 16-bit counter is cleared upon edge detection of the TIAAn0 pin, or TIAAn1 respectively.
Page 357 16-Bit Timer/Event Counter AA Chapter 10 Pulse period measurement The pulse period of a signal can be measured in the pulse width measurement mode, when the edge detection of one of the inputs TIAAn0 and TIAAn1 is set either to “rising edge” or “falling edge”. The detection of the other input should be set to “no edge detection”.
Page 358 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH FFFFH 16-bit counter TIAAn0 TAAnCC0 0000H INTTAAnCCR0 cleared by writing 0 TAAnOVF from CPU INTTAAnOV Figure 10-29 Basic Operation Timing of Pulse Period Measurement (TAAnOE0 = 0, TAAnOE1 = 0, TAAnOL0 = 0, TAAnOL1 = 0) : Values captured to TAAnCCR0 register (0000H to FFFFH) TIAAn0: Set to detection of rising edge (TAAnIS1, TAAnIS0 = 01B) TIAAn1: Set to no edge detection (TAAnIS3, TAAnIS2 = 00B)
Page 359 16-Bit Timer/Event Counter AA Chapter 10 Alternating pulse width and pulse space measurement The pulse period of a signal can be measured in the pulse width measurement mode alternating in one capture register, when the edge detection of one of the inputs TIAAn0 and TIAAn1 is set to “both rising and falling edges”.
Page 360 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH FFFFH 16-bit counter TIAAn0 TAAnCCR0 0000H INTTAAnCC0 cleared by writing 0 TAAnOVF from CPU INTTAAnOV Figure 10-31 Basic Operation Timing of Alternating Pulse Width and Pulse Space Measurement (TAAnOE0 = 0, TAAnOE1 = 0, TAAnOL0 = 0, TAAnOL1 = 0) Values captured to TAAnCCR0 register (0000H to FFFFH) TIAAn0: Set to detection of both rising and falling edges (TAAnIS1, TAAnIS0 = 11B)
Page 361 16-Bit Timer/Event Counter AA Chapter 10 Simultaneous pulse width and pulse space measurement Pulse width and pulse space can be measure simultaneously in the pulse width measurement mode, when the signal is input to both inputs TIAAn0 and TIAAn1, where both inputs detect opposite edges. By detection of the specified edge the resulting values of pulse width or pulse space are captured in the corresponding capture registers (TAAnCCR0, TAAnCCR1), and the timer is cleared and restarts counting.
Page 362 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH FFFFH 16-bit counter Note TIAAn0, TIAAn1 TAAnCCR0 0000H 0000H TAAnCCR1 INTTAAnCC0 INTTAAnCC1 cleared by writing 0 TAAnOVF from CPU INTTAAnOV Figure 10-33 Basic Operation Timing of Simultaneous Pulse Width and Pulse Space Measurement (TAAnOE0 = 0, TAAnOE1 = 0, TAAnOL0 = 0, TAAnOL1 = 0) Note...
Page 363: 32-Bit Capture In Free-Running Cascade Mode
16-Bit Timer/Event Counter AA Chapter 10 10.6.9 32-bit Capture in Free-Running Cascade Mode Two Timer AA (TAA0 in combination with TAA1, or TAA2 in combination with TAA3) can be cascaded to operate as a 32-bit capture timer. In cascade mode, the timer with the lower number (TAA0 or TAA2) is used to control the operation (master timer).
Page 364 Chapter 10 16-Bit Timer/Event Counter AA Note m = 0, 2 n = 1, 3 The 32-bit capture in cascade free-running mode is not available for TAA4. Explanation of signals can be found in Figure 10-1 on page 307. Block diagrams of the input circuits can be found in Figure 10-2 on page 308 to Figure 10-3 on page 308, Figure 10-34 shows the block diagram of TAAm and TAAn in cascade mode.
Page 365 16-Bit Timer/Event Counter AA Chapter 10 START Initial settings for upper 16-bit Timer (TMAAn) Free-running mode setting • (TAAnCTL1: TAAnMD[2:0] = 101B) • Set Capture operation (TAAnOPT0: TAAnCCS[1:0] = 11B) • Set Cascade operation (TAAnOPT1: TAAnCSE = 1) Initial settings for lower 16-bit Timer (TMAAm) •...
Page 366 Chapter 10 16-Bit Timer/Event Counter AA TAAmCE = 1 FFFFH 16-bit counter TMAAm FFFFH 16-bit counter TMAAn 0002H 0001H 0000H TIAAm0 0000H TAAmCCR0 0000H 0000H 0001H 0001H 0002H TAAnCCR0 TIAAm1 0000H TAAmCCR1 0000H TAAnCCR1 0000H 0002H 0002H INTTAAmCC0 INTTAAmCC1 INTTAAmOV INTTAAnOV TOAAm0 TOAAn0...
Page 367 16-Bit Timer/Event Counter AA Chapter 10 START Disable INTTAAmCCR0/1 Clear INTTAAmCCR0/1 pending flag Read TMAAnCCR0/1 and store as upper 16-bit capture value Read TMAAmCCR0/1 and store as lower 16-bit capture value. INTTAAmCCR0/1 pending? Enable INTTAAmCCR0/1 Figure 10-37 Flow of 32-bit Read (Capture or Counter Value) Disabling the capture interrupt (INTTAAmCCR0/1) is not required if the read sequence is done in the interrupt service routine, as nesting of the same interrupt is not possible.
Page 368: Capture Operation On Delayed Input Clock
Chapter 10 16-Bit Timer/Event Counter AA 10.6.10 Capture operation on delayed input clock If during capture operation the first capture event triggers before the first edge of the count clock occurs a value of FFFFH and not a value of 0000H may be stored in the TAAnCCRm registers.
Page 369 16-Bit Timer/Event Counter AA Chapter 10 User’s Manual U18743EE1V2UM00...
Page 370 Chapter 10 16-Bit Timer/Event Counter AA User’s Manual U18743EE1V2UM00...
Page 371: Chapter 11 16-Bit Interval Timer M
Chapter 11 16-Bit Interval Timer M The microcontroller includes a 16-bit interval Timer M (TMM0). 11.1 Features Timer M (TMM) supports only a clear & start mode. It does not support a free- running mode. To use Timer M in a manner equivalent to in the free-running mode, set the compare register to FFFF and start the 16-bit counter.
Page 372: Timer M Registers
Chapter 11 16-Bit Interval Timer M Internal bus TM0CTL0 TM0CE TM0CKS2 TM0CKS1 TM0CKS0 TM0CMP0 INTTM0EQ0 Controller 16-bit counter /8 or f /512 Clear INTWT Figure 11-1 Block diagram of Timer M 11.3 Timer M Registers TM0CMP0 - TMM0 compare register 0 The TM0CMP0 register is a 16-bit compare register.
Page 373 16-Bit Interval Timer M Chapter 11 TM0CTL0 - TMM0 control register 0 The TM0CTL0 register is an 8-bit register that controls the operation of TMM. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00 Address: FFFF F690 After Symbol...
Page 374: Operation
Chapter 11 16-Bit Interval Timer M Note : Main system clock frequency : Low frequency internal oscillator clock frequency (240 KHz) : High frequency internal oscillator clock frequency (8 MHz) : Sub oscillator frequency 11.4 Operation 11.4.1 Interval timer mode In the interval timer mode, a match interrupt signal (INTTM0EQ0) is output when the value of the 16-bit counter matches the value of TMM0 compare register 0 (TM0CMP0).
Page 375: Cautions
16-Bit Interval Timer M Chapter 11 11.4.2 Cautions Clock Generator and clock enable timing Because the second clock is the first pulse of the timer count-up signal when the TM0CE bit is changed from 0 to 1, the timer counts one clock less. Figure 11-3 Count operation start timing User’s Manual U18743EE1V2UM00...
Page 376 Chapter 11 16-Bit Interval Timer M User’s Manual U18743EE1V2UM00...
Page 377: Chapter 12 Timer Aa Synchroneous Operation
Chapter 12 Timer AA Synchroneous Operation Timers AA have a timer synchronized operation function, also named tuned operation mode. Master timer and incorporated slave timers of the corresponding timer group (listed in Table 12-1) start and clock synchronously. When the master timer is cleared, the slave timers are cleared synchronously, too.
Page 378 Chapter 12 Timer AA Synchroneous Operation Table 12-3 Timer output functions Triangular wave PWM Free-running mode PWM mode mode Synch Timer channel Synch Synch Synch Synch Synch Synch TOAA00 Toggle Toggle Toggle Toggle TAA0 (master) TOAA01 Toggle Toggle TOAA10 Toggle Toggle Toggle TAA1...
Page 379: Chapter 13 Watch Timer Functions
Chapter 13 Watch Timer Functions 13.1 Functions The Watch Timer has the following functions. • Watch Timer • Interval timer The Watch Timer and interval timer functions can be used at the same time. Reset Clear 5-bit counter INTWT Note 1 11-bit prescaler Clear INTWTI...
Page 380: Configuration
Chapter 13 Watch Timer Functions Watch Timer The Watch Timer generates interrupt requests (INTWT) at time intervals of 0.5 or 0.25 seconds by using the Sub oscillator (nominal f = 32.768 KHz). Caution When using a clock f obtained by dividing the main clock f by Prescaler3 as the Watch Timer count clock f , set the PRSM0 and PRSCM0 registers...
Page 381: Control Registers
Watch Timer Functions Chapter 13 13.3 Control Registers The Watch Timer operation mode register (WTM) controls the Watch Timer. Before operating the Watch Timer, set the count clock and the interval time. WTM - Watch Timer operation mode register The WTM register enables or disables the count clock and operation of the Watch Timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag.
Page 382: Operation
Chapter 13 Watch Timer Functions WTM7 WTM3 WTM2 Selection of set time of watch flag (0.5 s: f (0.25 s: f µ (977 s: f µ (488 s: f (0.5 s: f (0.25 s: f µ (977 s: f µ (488 s: f WTM1 Control of 5-bit counter operation...
Page 383: Operation As Interval Timer
Watch Timer Functions Chapter 13 13.4.2 Operation as interval timer The Watch Timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value. The interval time can be selected by the WTM4 to WTM7 bits of the WTM register.
Page 384: Cautions
Chapter 13 Watch Timer Functions 5-bit counter Overflow Overflow Start Count clock or f Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) Interval time (T) Figure 13-2 Operation Timing of Watch Timer/Interval Timer Note...
Page 385: Chapter 14 Watchdog Timer 2
Chapter 14 Watchdog Timer 2 14.1 Functions Watchdog Timer 2 has the following functions. • Default-start Watchdog Timer • Reset mode: Reset operation upon overflow of Watchdog Timer 2 (generation of WDT2RES signal) • Non-maskable interrupt request mode: NMI operation upon overflow of Watchdog Timer 2 (generation of INTWDT2 signal) •...
Page 386: Configuration
Chapter 14 Watchdog Timer 2 to f to f INTWDT2 /128 Clock 16-bit Output Selector input counter controller WDT2RES controller (internal reset signal) Clear WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 RUN2 Watchdog timer mode Watchdog timer enable register 2 (WDTM2) register (WDTE) Internal bus Figure 14-1...
Page 387: Control Registers
Watchdog Timer 2 Chapter 14 14.3 Control Registers WDTM2 - Watchdog Timer 2 mode register The WDTM2 register sets the operation mode, operation clock and overflow time of Watchdog Timer 2. Access The register can be read/written in 8-bit units. This register can be read any number of times, but it can be written only once following reset release.
Page 388 Chapter 14 Watchdog Timer 2 Table 14-3 Watchdog Timer 2 Clock Selection Selected WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 240 KHz (typ.) clock period 17.1 ms 34.1 ms 68.3 ms 136.5 ms 273.1 ms 546.1 ms 1,092.3 ms 2,184.5 ms (default) = 4 MHz = 16 MHz 16.4 ms...
Page 389: Watchdog Timer Operation
Watchdog Timer 2 Chapter 14 WDTE - Watchdog Timer enable register The counter of Watchdog Timer 2 is cleared and counting restarted by writing to the WDTE register. Access The register can be read/written in 8-bit units. Address FFFF F6D1 Initial Value .
Page 390: Watchdog Timer Operation In Power Save Mode
Chapter 14 Watchdog Timer 2 14.5 Watchdog Timer Operation in Power Save Mode If the Watchdog Timer overflows while the device is in power save mode, following procedures take place: • Watchdog Timer in reset operation mode (WDTM2.WDM21 = 1): A device RESET is executed.
Page 391: Chapter 15 Asynchronous Serial Interface (Uartd)
Chapter 15 Asynchronous Serial Interface (UARTD) The V850ES/Fx3-L microcontrollers have following instances of the Universal Asynchronous Serial Interface UARTD: UARTD V850ES/FE3-L V850ES/FF3-L V850ES/FG3-L Instances Names UARTD0 to UART1 UARTD0 to UART2 Throughout this chapter, the individual instances of UARTD are identified by “n”, for example, UDnCTL0 for the UARTDn control register 0.
Page 392: Configuration
Chapter 15 Asynchronous Serial Interface (UARTD) • On-chip dedicated baud rate generator • MSB-/LSB-first transfer selectable • Transmit/receive data inverted input/output possible • 13 to 20 bits selectable for the SBF (Sync Break Field) in the LIN (Local Interconnect Network) communication format –...
Page 393 Asynchronous Serial Interface (UARTD) Chapter 15 UARTDn consists of the following hardware units. Table 15-1 Configuration of UARTDn Item Configuration Registers UARTDn control register 0 (UDnCTL0) UARTDn control register 1 (UDnCTL1) UARTDn control register 2 (UDnCTL2) UARTDn option control register 0 (UDnOPT0) UARTDn status register (UDnSTR) UARTDn receive shift register UARTDn receive data register (UDnRX)
Page 394 Chapter 15 Asynchronous Serial Interface (UARTD) UARTDn receive data register (UDnRX) The UDnRX register is an 8-bit register that holds receive data. When 7 characters are received, 0 is stored in the highest bit (when data is received LSB first). In the reception enabled status, receive data is transferred from the UARTDn receive shift register to the UDnRX register in synchronization with the completion of shift-in processing of 1 frame.
Page 395: Uartd Registers
Asynchronous Serial Interface (UARTD) Chapter 15 15.3 UARTD Registers UDnCTL0 - UARTDn control register 0 The UDnCTL0 register is an 8-bit register that controls the UARTDn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 10H.
Page 396 Chapter 15 Asynchronous Serial Interface (UARTD) UDnDIR Transfer direction selection MSB-first transfer LSB-first transfer This register can be rewritten only when the UDnPWR bit = 0 or the UDnTXE bit = the UDnRXE bit = 0. When the transmission/reception is performed in the LIN format, set the UDnDIR bit to 1.
Page 397 Asynchronous Serial Interface (UARTD) Chapter 15 UDnOPT0 - UARTDn option control register 0 The UDnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTDn register. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 14H..
Page 398 Chapter 15 Asynchronous Serial Interface (UARTD) UDnSTT SBF transmission trigger Note SBF transmition trigger • This is the SBF transmittion trigger bit during LIN communication, and when read, “0” is always read. • Set the UDnSTT bit after setting the UDnPWR bit = UDnTXE bit = 1. Note To cancel the SBF reception enable status without receiving the SBF, set the UDnPWR bit = 0 or UDnRXE bit = 0.
Page 399 Asynchronous Serial Interface (UARTD) Chapter 15 UDnOPT1 - UARTDn option control register 1 The UDnOPT1 register is an 8-bit register that controls the serial transfer operation of the UARTDn register. This register can be read or written in 8-bit units. Reset input sets this register to 00H.
Page 400 Chapter 15 Asynchronous Serial Interface (UARTD) UDnSTR - UARTDn status register The UDnSTR register is an 8-bit register that displays the UARTDn transfer status and reception error contents. This register can be read or written in 8-bit or 1-bit units, but the UDnTSF bit is a read-only bit, while the UDnSSF, UDnDCE, UDnPE, UDnFE, and UDnOVE bits can both be read and written.
Page 401 Asynchronous Serial Interface (UARTD) Chapter 15 UDnSSF SBF receive successful flag When the UDnPWR bit = 1or the UDnRXE bit = 0 or the UDnSRS bit = 0 or the UDnSSF bit = 0 has been set When a consecutive low level (SBF) of 11 bits or more is received and the SBF reception mode bit UDnSRS has been set.
Page 402 Chapter 15 Asynchronous Serial Interface (UARTD) UDnRX - UARTDn receive data register The UDnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UDnRX register upon completion of reception of 1 byte of data.
Page 403: Interrupt Request Signals
Asynchronous Serial Interface (UARTD) Chapter 15 15.4 Interrupt Request Signals The following three interrupt request signals are generated from UARTDn. • Reception complete interrupt request signal (INTUDnR) • Status interrupt request signal (INTUDnS) • Transmission enable interrupt request signal (INTUDnT) Reception complete interrupt request signal (INTUDnR) A reception complete interrupt request signal is output when data is shifted into the receive shift register and transferred to the UDnRX register in the reception...
Page 404: Operation
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5 Operation 15.5.1 Data format Full-duplex serial data reception and transmission is performed. As shown in the figures below, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of MSB/LSB-first transfer are performed using the UDnCTL0 register.
Page 405 Asynchronous Serial Interface (UARTD) Chapter 15 (c) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H, TXDDn inversion 1 data frame Start Parity Stop (d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H 1 data frame Start Parity...
Page 406: Sbf Transmission/Reception Format
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5.2 SBF transmission/reception format The UARTD has an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. About LIN LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network.
Page 407 Asynchronous Serial Interface (UARTD) Chapter 15 A transmission enable interrupt request signal (INTUDnT) is output at the start of each transmission. The INTUDnT signal is also output at the start of each SBF transmission. Wake-up Synch Check signal break Synch DATA DATA Ident...
Page 408: Sbf Transmission
Chapter 15 Asynchronous Serial Interface (UARTD) Check-sum field distinctions are made by software. UARTDn is initialized following CSF reception, and the processing for setting the SBF reception mode again is performed by software. When the UDnSRS bit = 1, the SBF reception can be performed automatically without setting to the SBF reception mode again.
Page 409 Asynchronous Serial Interface (UARTD) Chapter 15 bits is suppressed and UART communication error detection processing is not performed. Moreover, data transfer of the UARTDn reception shift register and UDnRX register is not performed and FFH, the initial value, is held. If the SBF width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the SBF reception mode is returned to.
Page 410: Data Consistency Check
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5.5 Data consistency check The UARTD incorporates a data consistency check function to detect a mismatch between the transmit data written to transmit register (UDnTX) and the data on the bus when the device operates in master mode. The data consistency is checked by comparing the transmit data in the transmit register (UDnTX) and the receive data in the receive register (UDnRX).
Page 411 Asynchronous Serial Interface (UARTD) Chapter 15 (b) Timing example of data consistency error when there is a delay between transmit and receive operation Communication stops UDnTX signal Start Stop 0xD5 UDnRX signal Start Stop 0xAA UDnSTR. Reception UDnTSF internal error detection UDnSTR.
Page 412: Uart Transmission
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5.6 UART transmission First, set the transmission enabled status by performing the following procedures. • Specify the operation clock by the UARTD control register 1 (UDnCTL1) • Specify the baud rate by the UARTD control register 2 (UDnCTL2) •...
Page 413: Continuous Transmission Procedure
Asynchronous Serial Interface (UARTD) Chapter 15 15.5.7 Continuous transmission procedure UARTDn can write the next transmit data to the UDnTX register when the UARTDn transmit shift register starts the shift operation. The transmit timing of the UARTDn transmit shift register can be judged from the transmission enable interrupt request signal (INTUDnT).
Page 414: Uart Reception
Chapter 15 Asynchronous Serial Interface (UARTD) Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDDn UDnTX Data (1) Data (2) Data (3) Transmission Data (2) Data (1) shift register INTUDnT UDnTSF Figure 15-6 Continuous transmission operation timing —transmission start Stop UDTTXD Parity...
Page 415 Asynchronous Serial Interface (UARTD) Chapter 15 • Specify the communication direction, parity, data character length, and stop bit length by the UARTD control register 0 (UDnCTL0). • Set the power bit and the reception enabled bit (UDnPWR = 1, UDnRXE = When the sampling of the input level of the RXDDn pin is performed and the falling edge is detected, the data sampling of the RXDDn input is started.
Page 416: Reception Errors
Chapter 15 Asynchronous Serial Interface (UARTD) and the UDnPWR bit = 0 or UDnRXE bit = 0 conflict, the INTUDnR signal may be generated in spite of these being no data stored in the UDnRX register. To complete reception without waiting INTUDnR signal generation, be sure to clear (0) the interrupt request flag (UDnRIF) of the UDnRIC register, after setting (1) the interrupt mask flag (UDnRMK) of the interrupt control register (UDnRIC) and then set (1) the UDnPWR bit = 0 or UDnRXE bit = 0.
Page 417 Asynchronous Serial Interface (UARTD) Chapter 15 The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side. In the case of even parity and odd parity, it is possible to detect odd-count bit errors.
Page 418: Receive Data Noise Filter
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5.11 Receive data noise filter This filter samples the RXDDn pin using the base clock of the prescaler output. When the same sampling value is read twice, the match detector output changes and the RXDDn signal is sampled as the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see Figure 15-10).
Page 419: Baud Rate Generator
Asynchronous Serial Interface (UARTD) Chapter 15 15.6 Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTDn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel.
Page 420 Chapter 15 Asynchronous Serial Interface (UARTD) UDnCTL1 - UARTDn control register 1 The UDnCTL1 register is an 8-bit register that selects the UARTDn base clock. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Caution Clear the UDnCTL0.UDnPWR bit to 0 before rewriting the UDnCTL1 register.
Page 421 Asynchronous Serial Interface (UARTD) Chapter 15 UDnCTL2 - UARTDn control register 2 The UDnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTDn. This register can be read or written in 8-bit units. Reset input sets this register to FFH.
Page 422 Chapter 15 Asynchronous Serial Interface (UARTD) Baud rate error The baud rate error is obtained by the following equation. Actual baud rate (baud rate with error) --------------------------------------------------------------------------- - × – Error (%) 100 [%] Target baud rate (correct baud rate) Caution The baud rate error during transmission must be within the error tolerance on the receiving side.
Page 423 Asynchronous Serial Interface (UARTD) Chapter 15 Table 15-4 Baud rate generator setting data (normal operation, f = 16 MHz, PRSI = 0) Target Actual UDnCTL1 UDnCTL2 Baud rate error baud rate baud rate [bps] [bps] Selector Divider Divider k 300.48 0.16 600.96 0.16...
Page 424 Chapter 15 Asynchronous Serial Interface (UARTD) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation.
Page 425 Asynchronous Serial Interface (UARTD) Chapter 15 Similarly, obtaining the following maximum allowable transfer rate yields the following. 21k 2 – × × × × ----- - ----------- - ------------------ - FLmax 11 FL – 21k 2 – × × ------------------ - FL 11 FLmax Therefore, the minimum baud rate that can be received by the destination is as...
Page 426: Cautions
Chapter 15 Asynchronous Serial Interface (UARTD) Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result.
Page 427: Chapter 16 Clocked Serial Interface (Csib)
Chapter 16 Clocked Serial Interface (CSIB) The V850ES/Fx3-L microcontrollers have following instances of the Clocked Serial Interface CSIB: CSIB V850ES/FE3-L V850ES/FF3-L V850ES/FG3-L Instances Names CSIB0 to CSIB1 Throughout this chapter, the individual instances of CSIB are identified by “n”, for example, CBnCTL0 for the CSIBn control register 0. 16.1 Features •...
Page 428: Configuration
Chapter 16 Clocked Serial Interface (CSIB) 16.2 Configuration The following shows the block diagram of CSIBn. Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR INTCBnT Controller INTCBnR Phase control (n=0) or TOAA01(n=1) or /128(n=2,3) CBnTX SCKBn Phase SO latch SOBn control SIBn Shif t register CBnRX Figure 16-1...
Page 429 Clocked Serial Interface (CSIB) Chapter 16 CBnRX - CSIBn receive data register The CBnRX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. The receive operation is started by reading the CBnRX register in the reception enabled status.
Page 430: Csib Control Registers
Chapter 16 Clocked Serial Interface (CSIB) 16.3 CSIB Control Registers The following registers are used to control CSIBn. • CSIBn control register 0 (CBnCTL0) • CSIBn control register 1 (CBnCTL1) • CSIBn control register 2 (CBnCTL2) • CSIBn status register (CBnSTR) CBnCTL0 - CSIBn control register 0 CBnCTL0 is a register that controls the CSIBn serial transfer operation.
Page 431 Clocked Serial Interface (CSIB) Chapter 16 CBnSCE Specification of start transfer disable/enable Reception start trigger invalid Recepetion start trigger valid This bit controls the behaviour upon a communication start trigger in master/slave single/continuous reception mode. To start the reception operation set the bit to 1 before performing a dummy read to the CBnRX register.
Page 432 Chapter 16 Clocked Serial Interface (CSIB) CBnCTL1 - CSIBn control register 1 CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0.
Page 433 Clocked Serial Interface (CSIB) Chapter 16 Note PRSI can be set by the option bytes: Refer to “Flash Memory” on page 259 for details. CBnCTL2 - CSIBn control register 2 CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits.
Page 434 Chapter 16 Clocked Serial Interface (CSIB) Transfer data length The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits change function using the CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
Page 435 Clocked Serial Interface (CSIB) Chapter 16 CBnSTR - CSIBn status register CBnSTR is an 8-bit register that displays the CSIBn status. This register can be read or written in 8-bit or 1-bit units, but the CBnTSF flag is read-only. Reset input clears this register to 00H. In addition to reset input, the CBnSTR register can be initialized by clearing (0) the CBnCTL0.CBnPWR bit.
Page 436: Operation
Chapter 16 Clocked Serial Interface (CSIB) 16.4 Operation 16.4.1 Single transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.3 (2) CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnTX write (55H) CBnRX read (AAH)
Page 437 Clocked Serial Interface (CSIB) Chapter 16 Note In single transmission or single transmission/reception mode, the INTCBnT signal is not generated. When communication is complete, the INTCBnR signal is generated. The processing of steps (3) and (4) can be set simultaneously. Caution In case the CSIB interface is operating in •...
Page 438: Single Transfer Mode (Master Mode, Reception Mode)
Chapter 16 Clocked Serial Interface (CSIB) 16.4.2 Single transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.3 (2) CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnRX read (55H) CBnRX read (AAH) SCKBn...
Page 439: Continuous Mode (Master Mode, Transmission/Reception Mode)
Clocked Serial Interface (CSIB) Chapter 16 16.4.3 Continuous mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 3 (see 16.3 (2) CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnTX SCKBn SOBn...
Page 440: Continuous Mode (Master Mode, Reception Mode)
Chapter 16 Clocked Serial Interface (CSIB) (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of transmission/reception). To continue transfer, repeat steps (5) to (7) before (8). In transmission mode or transmission/reception mode, the communication is not started by reading the CBnRX register.
Page 441: Continuous Reception Mode (Error)
Clocked Serial Interface (CSIB) Chapter 16 (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of reception). To continue transfer, repeat steps (5) and (6) before (7). 16.4.5 Continuous reception mode (error) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (see 16.3 (2) CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits...
Page 442: Continuous Mode (Slave Mode, Transmission/Reception Mode)
Chapter 16 Clocked Serial Interface (CSIB) (8) Overrun error processing is performed after checking that the CBnOVE bit = 1 in the INTCBnR interrupt servicing. (9) Clear CBnOVE bit to 0. (10)Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation CSIBn (end of reception).
Page 443 Clocked Serial Interface (CSIB) Chapter 16 (3) Set the CBnTXE, CBnRXE and CBnSCE bits of the CBnCTL0 register to 1 at the same time as specifying the transfer mode using the CBnDIR bit, to set the transmission/reception enabled status. (4) Set the CBnPWR bit to 1 to enable supply of the CSIBn operation. (5) Write the transfer data to the CBnTX register.
Page 444 Chapter 16 Clocked Serial Interface (CSIB) Discontinued In case the CSIB is operating in continuous slave transmission mode transmission (CBnCTL0.CBnTMS = 1, CBnCTL1.CBnCKS[2:0] = 111 ) and new data is not written to the CBnTX register the SOBn pin outputs the level of the last bit. Figure 16-4 outlines this behaviour.
Page 445: Continuous Mode (Slave Mode, Reception Mode)
Clocked Serial Interface (CSIB) Chapter 16 16.4.7 Continuous mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.3 (2) CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) SCKBn SIBn INTCBn R...
Page 446: Clock Timing
Chapter 16 Clocked Serial Interface (CSIB) 16.4.8 Clock timing SCKBn SIBn capture SOBn Reg-R/W INTCBnT interrupt Note INTCBnR interrupt Note CBnTSF Figure 16-5 (i) Communication type 1 (CBnCKP = 0, CBnDAP = 0) SCKBn SIBn capture SOBn Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2...
Page 447 Clocked Serial Interface (CSIB) Chapter 16 SCKBn SIBn capture SOBn Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF Figure 16-7 (iii) Communication type 2 (CBnCKP = 0, CBnDAP = 1) SCKBn SIBn capture SOBn Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2...
Page 448: Output Pins
Chapter 16 Clocked Serial Interface (CSIB) 16.5 Output Pins SCKBn pin When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows. CBnCKP CBnCKS2 CBnCKS1 CBnCKS0 SCKBn pin output Don’t care Don’t care Don’t care Fixed to high level High impedance Other than above...
Page 449: Operation Flow
Clocked Serial Interface (CSIB) Chapter 16 16.6 Operation Flow Single transmission START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnT interrupt signal? Data to be transferred next exists? CBnTSF bit = 1? (CBnSTR) CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting.
Page 450 Chapter 16 Clocked Serial Interface (CSIB) Single reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) CBnRX register dummy read (start reception) INTCBnR interrupt signal? Last data? CBnRX register read CBnSCE bit = 0 (CBnCTL0) CBnRX register read CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting.
Page 451 Clocked Serial Interface (CSIB) Chapter 16 Single transmission/reception START Note 1 Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnR interrupt signal? Transmission/reception Reception Transmission Read CBnRX register. Read CBnRX register. Transfer end? Transfer end? Transfer end? Note 2 Note 2 Note 2...
Page 452 Chapter 16 Clocked Serial Interface (CSIB) Continuous transmission START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnT interrupt signal? Data to be transferred next exists? CBnTSF bit = 1? (CBnSTR) CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting.
Page 453 Clocked Serial Interface (CSIB) Chapter 16 Continuous reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) CBnRX register dummy read (start reception) INTCBnR bit = 1? CBnRX register read CBnOVE bit = 1? (CBnSTR) CBnRX register read Is data being received last data? CBnOVE bit clear (CBnSTR)
Page 454 Chapter 16 Clocked Serial Interface (CSIB) Continuous transmission/reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register. INTCBnT interrupt signal? Is data being transferred last data? Write CBnTX register. INTCBnR interrupt signal? CBnRX register read CBnOVE bit = 0? (CBnSTR) CBnOVE bit clear (CBnSTR)
Page 455 Clocked Serial Interface (CSIB) Chapter 16 Caution When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading the CBnSTR.CBnOVE bit after DMA transfer has been completed.
Page 456 Chapter 16 Clocked Serial Interface (CSIB) User’s Manual U18743EE1V2UM00...
Page 457: Chapter 17 I C Bus (Iic)
Chapter 17 I C Bus (IIC) This microcontroller has one instance of this I C Bus interface. Note Throughout this chapter, the individual instances of this I C Bus interface identified by “n” (n = 0). 17.1 Features The I²C provides a synchronous serial interface with the following features: •...
Page 458: Configuration
Chapter 17 C Bus (IIC) 17.3 Configuration The block diagram of the I Cn is shown below. Figure 17-1 Block diagram of I Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn LRELn WRELnSPIEn WTIMn ACKEn STTn SPTn...
Page 459 C Bus (IIC) Chapter 17 A serial bus configuration example is shown below. Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC Address 4 Slave IC Address N Figure 17-2 Serial bus configuration example using I...
Page 460 Chapter 17 C Bus (IIC) IIC shift register n (IICn) The IICn register converts 8-bit serial data into 8-bit parallel data and vice versa, and can be used for both transmission and reception. Write and read operations to the IICn register are used to control the actual transmit and receive operations.
Page 461 C Bus (IIC) Chapter 17 (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the SCL0n pin. (12) Start condition generator A start condition is issued when the IICCn.STTn bit is set. However, in the communication reservation disabled status (IICFn.IICRSVn = 1), this request is ignored and the IICFn.STCFn bit is set if the bus is not released (IICFn.IICBSYn = 1).
Page 462: Iic Registers
Chapter 17 C Bus (IIC) 17.4 IIC Registers The I C interfaces are controlled by the following registers. • IIC control registers IICCn • IIC status registers IICSn • IIC flag registers IICFn • IIC clock select registers IICCLn • IIC function expansion registers IICXn •...
Page 463 C Bus (IIC) Chapter 17 IICCn - IICn control registers The IICCn registers enable/stop I Cn operations, set the wait timing, and set other I C operations. These registers can be read or written in 8-bit or 1-bit units. Set the SPIE0, WTIM0, and ACKE0 bits when the IICE bit is 0 or during the wait period.
Page 464 Chapter 17 C Bus (IIC) SPIEn Enable/disable generation of interrupt request when stop condition is detected Disabled Enabled Note 2 Condition for clearing (SPIEn = 0) Condition for setting (SPIEn = 1) • Cleared by instruction • Set by instruction •...
Page 465 C Bus (IIC) Chapter 17 STTn Start condition trigger Start condition is not generated. When bus is released (in STOP mode): A start condition is generated (for starting as master). The SDA0n line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, the SCL0n line is changed to low level.
Page 466 Chapter 17 C Bus (IIC) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until it goes to high level.
Page 467 C Bus (IIC) Chapter 17 IICSn - IICn status registers The IICSn registers indicate the status of the I Cn bus. These registers are read-only, in 8-bit or 1-bit units. The IICS0 register can only be read when the IICC0.STT0 bit is 1 or during the wait period.
Page 468 Chapter 17 C Bus (IIC) EXCn Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXCn = 0) Condition for setting (EXCn = 1) • When a start condition is detected • When the higher four bits of the received address data are either “0000”...
Page 469 C Bus (IIC) Chapter 17 ACK was detected. Condition for clearing (ACKDn = 0) Condition for setting (ACKD = 1) • When a stop condition is detected • After the SDA0n bit is set to low level at the rising edge of the SCL0n pin’s ninth clock •...
Page 470 Chapter 17 C Bus (IIC) IICFn - IICn flag registers The registers set the I Cn operation mode and indicate the I C bus status. These registers can be read or written in 8-bit or 1-bit units. However, the STCFn and IICBSYn bits are read-only. IICRSVn enables/disables the communication reservation function.
Page 471 C Bus (IIC) Chapter 17 IICRSVn Communication reservation function disable bit Communication reservation enabled Communication reservation disabled Condition for clearing (IICRSVn = 0) Condition for setting (IICRSVn = 1) • Clearing by instruction • Setting by instruction • After reset Note Bits 6 and 7 are read-only bits.
Page 472 Chapter 17 C Bus (IIC) IICCLn - IICn clock select registers The IICCLn registers set the transfer clock for the I Cn bus. These registers can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only. The SMCn, CLn1, and CLn0 bits are set by the combination of the IICXn.CLXn bit and the OCKSTHn, OCKSn[1:0] bits of the OCKSn register (see “Transfer rate setting”...
Page 473 C Bus (IIC) Chapter 17 IICXn - IICn function expansion registers The IICXn registers provide additional transfer data rate configuration in fast- speed mode. Setting of the IICXn.CLXn is performed in combination with the IICCLn.SMCn, IICCLn.CLn[1:0], OCKSn.OCKSTHn and OCKSn.OCKSn[1:0] (refer to “Transfer rate setting” on page 475) Reset input clears these registers to 00 After reset: 00 Address:...
Page 474 Chapter 17 C Bus (IIC) OCKSn - IICn division clock select registers The OCKSn registers control the I Cn division clock. These registers can be read or written in 8-bit units. RESET input sets this register to 00H. After reset: 00H Address: OCKS0 FFFFF340 OCKSn...
Page 475 C Bus (IIC) Chapter 17 Transfer rate setting The nominal transfer rate of the I C interface is determined by the root clock source f . The frequency of fXP1 can be set to fXP1or fXP1/2 by the PRSI bit of the option byte (007BH). •...
Page 476 Chapter 17 C Bus (IIC) Table 17-3 PRSI = 0: Transfer rate settings in fast-speed mode (IICCLn.SMCn = 1) Possible Main System IICXn. IICCLn. IICCLn. Selected Transfer (Reference) Clock Range (fxx) OCKSn CLXn CLn1 CLn0 Clock Clock Transfer speed from fxx/2 fxx/48 8 MHz...
Page 477 C Bus (IIC) Chapter 17 Table 17-5 PRSI = 1: Transfer rate settings in fast-speed mode (IICCLn.SMCn = 1) Possible Main System IICXn. IICCLn. IICCLn. Selected Transfer (Reference) Clock Range (fxx) OCKSn CLXn CLn1 CLn0 Clock Clock Transfer speed from fxx/4 fxx/96 16 MHz...
Page 478 Chapter 17 C Bus (IIC) Clock Stretching Heavy capacitive load and the dimension of the external pull-up resistor on the C bus pins may yield extended rise times of the rising edge of SCLn and SDAn. Since the controller senses the level of the I C bus signals it recognizes such situation and takes countermeasures by stretching the clock SCLn in order to ensure proper high level time t...
Page 479 C Bus (IIC) Chapter 17 IICn - IICn shift registers The IICn registers are used for serial transmission/reception (shift operations) synchronized with the serial clock. These registers can be read or written in 8- bit units, but data should not be written to the IICn register during a data transfer.
Page 480: C Bus Mode Functions
Chapter 17 C Bus (IIC) 17.5 I C Bus Mode Functions 17.5.1 Pin functions The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows. SCL0n This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices.
Page 481: C Bus Definitions And Control Methods
C Bus (IIC) Chapter 17 17.6 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. The transfer timing for the “start condition”, "address", "transfer direction specification", "data"...
Page 482: Addresses
Chapter 17 C Bus (IIC) Caution When the IICC0.IICE0 bit of the microcontroller is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. Be sure to set the IICC0.IICE0 bit to 1 when the SCL00 and SDA00 lines are high level.
Page 483: Transfer Direction Specification
C Bus (IIC) Chapter 17 17.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 484 Chapter 17 C Bus (IIC) the ACKEn bit to 0 will prevent the master device from starting transmission of the subsequent data. Similarly, when the master device is receiving (when TRCn bit = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, clearing the ACKEn bit to 0 will prevent the ACK signal from being returned.
Page 485: Stop Condition
C Bus (IIC) Chapter 17 17.6.5 Stop condition When the SCL0n pin is high level, changing the SDA0n pin from low level to high level generates a stop condition. A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed.
Page 486: Wait Signal (Wait)
Chapter 17 C Bus (IIC) 17.6.6 Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0n pin to low level notifies the communication partner of the wait status.
Page 487 C Bus (IIC) Chapter 17 When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn bit = 1) Master and slave both wait Master after output of ninth clock. IICn data write (cancel wait) IICn SCL0n Slave...
Page 488: C Interrupt Request Signals (Intiicn)
Chapter 17 C Bus (IIC) 17.7 I C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing. 17.7.1 Master device operation Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1>...
Page 489 C Bus (IIC) Chapter 17 Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 STTn bit = 1 SPTn bit = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 490 Chapter 17 C Bus (IIC) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ♦ AD6 to AD0 D7 to D0 D7 to D0 ♦ ♦ ♦ ♦...
Page 491: Slave Device Operation
C Bus (IIC) Chapter 17 17.7.2 Slave device operation Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ♦ ♦ ♦ ∆4 ♦ 1: IICSn register = 0001X110B ♦...
Page 492 Chapter 17 C Bus (IIC) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 493 C Bus (IIC) Chapter 17 Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 494 Chapter 17 C Bus (IIC) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 495: Slave Device Operation (When Receiving Extension Code)
C Bus (IIC) Chapter 17 17.7.3 Slave device operation (when receiving extension code) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ♦ ♦ ♦ ∆4 ♦...
Page 496 Chapter 17 C Bus (IIC) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 497 C Bus (IIC) Chapter 17 Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop ♦ ♦ ♦ ♦ ∆5 ♦ 1: IICSn register = 0010X010B ♦ 2: IICSn register = 0010X000B ♦ 3: IICSn register = 0010X010B ♦...
Page 498 Chapter 17 C Bus (IIC) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 499: Operation Without Communication
C Bus (IIC) Chapter 17 17.7.4 Operation without communication Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 ∆1 ∆ 1: IICSn register = 00000001B Remarks 1. ∆: Generated only when SPIEn bit = 1 2.
Page 500 Chapter 17 C Bus (IIC) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ♦ ♦ ♦ ∆4 ♦ 1: IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing) ♦...
Page 501: Operation When Arbitration Loss Occurs
C Bus (IIC) Chapter 17 17.7.6 Operation when arbitration loss occurs When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0 D7 to D0 ♦ ∆2 ♦ 1: IICSn register = 01000110B (Example: When ALDn bit is read during interrupt servicing) ∆...
Page 502 Chapter 17 C Bus (IIC) When arbitration loss occurs during data transfer <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ♦ ♦ ∆3 ♦ 1: IICSn register = 10001110B ♦ 2: IICSn register = 01000000B (Example: When ALDn bit is read during interrupt servicing) ∆...
Page 503 C Bus (IIC) Chapter 17 When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦ ♦ ∆3 ♦ 1: IICSn register = 1000X110B ♦...
Page 504 Chapter 17 C Bus (IIC) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition When WTIMn bit = 1 STTn bit = 1 ♦ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 ♦...
Page 505 C Bus (IIC) Chapter 17 When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition When WTIMn bit = 1 SPTn bit = 1 ♦ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 ♦...
Page 506: Interrupt Request Signal (Intiicn)
Chapter 17 C Bus (IIC) 17.8 Interrupt Request Signal (INTIICn) The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below. Table 17-6 INTIICn generation timing and wait control WTIMn Bit During Slave Device Operation During Master Device Operation...
Page 507: Address Match Detection Method
C Bus (IIC) Chapter 17 Wait cancellation method The four wait cancellation methods are as follows. • By setting the IICCn.WRELn bit to 1 • By writing to the IICn register • Note By start condition setting (IICCn.STTn bit = 1) •...
Page 508: Extension Code
Chapter 17 C Bus (IIC) 17.11 Extension Code • When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (IICSn.EXCn bit) is set for extension code reception and an interrupt request signal (INTIICn) is issued at the falling edge of the eighth clock.
Page 509: Arbitration
C Bus (IIC) Chapter 17 17.12 Arbitration When several master devices simultaneously output a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs.
Page 510: Wakeup Function
Chapter 17 C Bus (IIC) Table 17-8 Status during arbitration and interrupt request signal generation timing Status During Arbitration Interrupt Request Generation Timing Transmitting address transmission At falling edge of eighth or ninth clock following byte Note 1 transfer Read/write data after address transmission Transmitting extension code Read/write data after extension code transmission Transmitting data...
Page 511: Cautions
C Bus (IIC) Chapter 17 17.14 Cautions When IICFn.STCENn bit = 0 Immediately after the I Cn operation is enabled, the bus communication status (IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication.
Page 512: Communication Operations
Chapter 17 C Bus (IIC) 17.15 Communication Operations 17.15.1 Master operation 1 The following shows the flowchart for master communication when the communication reservation function is enabled (IICFn.IICRSVn bit = 0) and the master operation is started after a stop condition is detected (IICFn.STCENn bit = 0).
Page 513 C Bus (IIC) Chapter 17 START IICCLn ← ××H Select transfer clock IICCn ← ××H IICEn = SPIEn = WTIMn = SPTn = 1 INTIICn = 1? Yes (stop condition detection) STTn = 1 Wait time is secured by Wait software Communication reservation MSTSn = 1?
Page 514: Master Operation 2
Chapter 17 C Bus (IIC) 17.15.2 Master operation 2 The following shows the flowchart for master communication when the communication reservation function is disabled (IICRSVn bit = 1) and the master operation is started without detecting a stop condition (STCENn bit = 1). START IICCLn ←...
Page 515: Slave Operation
C Bus (IIC) Chapter 17 17.15.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIICn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary.
Page 516 Chapter 17 C Bus (IIC) Communication direction flag This flag indicates the direction of communication and is the same as the value of IICSn.TRCn bit. The following shows the operation of the main processing block during slave operation. Start I Cn and wait for the communication enabled status.
Page 517 C Bus (IIC) Chapter 17 START IICCLn ← XXH Selection of transfer flag IICFn ← XXH IICFn register setting IICCn ← XXH IICEn = 1 Communication mode? ACKEn = WTIMn = 1 Communication direction flag = 1? WRELn = 1 WTIMn = 1 Communication mode? Data processing...
Page 518 Chapter 17 C Bus (IIC) During an INTIICn interrupt, the status is confirmed and the following steps are executed. <1> When a stop condition is detected, communication is terminated. <2> When a start condition is detected, the address is confirmed. If the address does not match, communication is terminated.
Page 519: Timing Of Data Communication
C Bus (IIC) Chapter 17 17.16 Timing of Data Communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICSn.TRCn bit, which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 520 Chapter 17 C Bus (IIC) Processing by master device ← ← IICn IICn address IICn data ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transmit Transfer lines SCL0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0n Start condition Processing by slave device ←...
Page 521 C Bus (IIC) Chapter 17 Processing by master device ← ← IICn IICn data IICn data ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transmit Transfer lines SCL0n SDA0n Processing by slave device ← ← IICn IICn FFH Note IICn FFH Note...
Page 522 Chapter 17 C Bus (IIC) Processing by master device ← ← IICn IICn data IICn address ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn Transmit Transfer lines SCL0n SDA0n Stop Start condition condition Processing by slave device ←...
Page 523 C Bus (IIC) Chapter 17 Processing by master device ← ← IICn IICn address IICn FFH Note ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn Note INTIICn TRCn Transfer lines SCL0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0n Start condition Processing by slave device ←...
Page 524 Chapter 17 C Bus (IIC) Processing by master device IICn ← FFH Note IICn ← FFH Note IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn Note Note WRELn INTIICn TRCn Receive Transfer lines SCL0n SDA0n Processing by slave device IICn ←...
Page 525 C Bus (IIC) Chapter 17 Processing by master device ← ← IICn IICn FFH Note IICn address ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn Note WRELn INTIICn (When SPIEn = 1) TRCn Transfer lines SCL0n D7D6D5D4D3D2D1D0AD5 SDA0n N- ACK Stop Start condition...
Page 526 Chapter 17 C Bus (IIC) User’s Manual U18743EE1V2UM00...
Page 527: Chapter 18 Can Controller (Can)
Chapter 18 CAN Controller (CAN) These microcontrollers feature an on-chip n-channel CAN (Controller Area Network) controller that complies with the CAN protocol as standardized in ISO 11898. The number of CAN channels is given in the table below: V850ES/FE3-L V850ES/FF3-L V850ES/FG3-L Channels Names...
Page 528: Features
Chapter 18 CAN Controller (CAN) 18.1 Features • Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test) • Standard frame and extended frame transmission/reception enabled • Transfer rate: 1 Mbps max. (if CAN clock input ≥ 8 MHz, for 32 channels) •...
Page 529: Overview Of Functions
CAN Controller (CAN) Chapter 18 18.1.1 Overview of functions Table 18-1 presents an overview of the CAN Controller functions. Table 18-1 Overview of functions Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Maximum 1 Mbps (CAN clock input ≥ 8 MHz) Baud rate Data storage Storing messages in the CAN RAM...
Page 530: Configuration
18.1.2 Configuration The CAN Controller is composed of the following four blocks. • NPB interface This functional block provides an NPB (NEC Peripheral I/O Bus) interface and means of transmitting and receiving signals between the CAN module and the host CPU.
Page 531: Can Protocol
CAN Controller (CAN) Chapter 18 18.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer.
Page 532: Frame Types
Chapter 18 CAN Controller (CAN) 18.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 18-2 Frame types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Frame used to delay the next data frame or remote frame...
Page 533 CAN Controller (CAN) Chapter 18 Remote frame A remote frame is composed of six fields. Remote frame <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Figure 18-4 Remote frame Note...
Page 534 Chapter 18 CAN Controller (CAN) (b) Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Arbitration field (Control field) Identifier (r1) ID28 · · · · · · · · · · · · · · · · · · · · · · · · · · ID18 (11 bits) (1 bit) (1 bit)
Page 535 CAN Controller (CAN) Chapter 18 (c) Control field The control field sets “DLC” as the number of data bytes in the data field (DLC = 0 to 8). (Arbitration field) Control field (Data field) DLC3 DLC2 DLC1 DLC0 (IDE) Figure 18-8 Control field Note D: Dominant = 0...
Page 536 Chapter 18 CAN Controller (CAN) (d) Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. (Control field) Data field (CRC field) Data 0 Data 7 (8 bits) (8 bits)
Page 537 CAN Controller (CAN) Chapter 18 (f) ACK field The ACK field is used to acknowledge normal reception. (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit) Figure 18-11 ACK field Note D: Dominant = 0 R: Recessive = 1 •...
Page 538 Chapter 18 CAN Controller (CAN) Note Bus idle: State in which the bus is not used by any node. D: Dominant = 0 R: Recessive = 1 – Error passive node The interframe space consists of an intermission field, a suspend transmission field, and a bus idle field.
Page 539: Error Frame
CAN Controller (CAN) Chapter 18 18.2.4 Error frame An error frame is output by a node that has detected an error. Error frame (<4>) <1> <2> <3> (<5>) 6 bits 0 to 6 bits 8 bits Interframe space or overload frame Error delimiter Error flag 2 Error flag 1...
Page 540: Overload Frame
Chapter 18 CAN Controller (CAN) 18.2.5 Overload frame An overload frame is transmitted under the following conditions. • When the receiving node has not completed the reception operation • If a dominant level is detected at the first two bits during intermission •...
Page 541: Functions
CAN Controller (CAN) Chapter 18 18.3 Functions 18.3.1 Determining bus priority When a node starts transmission: • During bus idle, the node that output data first transmits the data. When more than one node starts transmission: • The node that consecutively outputs the dominant level for the longest from the first bit of the arbitration field has the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value).
Page 542: Multi Masters
Chapter 18 CAN Controller (CAN) 18.3.3 Multi masters As the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus master. 18.3.4 Multi cast Although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes.
Page 543 CAN Controller (CAN) Chapter 18 Output timing of error frame Table 18-12 Output timing of error frame Type Output timing Bit error, stuff error, Error frame output is started at the timing of the bit following form error, ACK error the detected error.
Page 544 Chapter 18 CAN Controller (CAN) Table 18-13 Types of error states Value of error Indication of Type Operation Operation specific to error state counter CnINFO register Error active Transmission 0 to 95 TECS1, TECS0 = 00 Outputs an active error flag (6 consecutive dominant-level bits) on detection of the error.
Page 545 CAN Controller (CAN) Chapter 18 (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counter is updated immediately after error detection. Table 18-14 Error counter Transmission error counter Reception error counter State (TEC7 to TEC0 bits)
Page 546 Chapter 18 CAN Controller (CAN) Recovery from bus-off state When the CAN module is in the bus-off state, the CAN module permanently sets its output signals (CTXDn) to recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence.
Page 547 CAN Controller (CAN) Chapter 18 TEC > FFH »bus-off« »bus-off-recovery-sequence« »error-active« »error-passive« BOFF bit in CnINFO register <1> <2> OPMODE[2:0] in CnCTRL ≠ 00H ≠ 00H register (user writings) <3> OPMODE[2:0] in CnCTRL ≠ 00H ≠ 00H register (user readings) TEC[7:0] 00H ≤...
Page 548 Chapter 18 CAN Controller (CAN) Initializing CAN module error counter register (CnERC) in initialization mode If it is necessary to initialize the CAN module error counter register (CnERC) and CAN module information register (CnINFO) for debugging or evaluating a program, they can be initialized to the default value by setting the CCERC bit of the CnCTRL register in the initialization mode.
Page 549: Baud Rate Control Function
CAN Controller (CAN) Chapter 18 18.3.7 Baud rate control function Prescaler The CAN controller has a prescaler that divides the clock (f ) supplied to CAN. This prescaler generates a CAN protocol layer basic system clock (f derived from the CAN module system clock (f ), and divided by 1 to 256 CANMOD (“CnBRP - CANn module bit rate prescaler register”...
Page 550 Chapter 18 CAN Controller (CAN) Data bit time(DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 Sample point (SPT) Figure 18-19 Configuration of data bit time defined by CAN specification Table 18-16 Configuration of data bit time defined by CAN specification Notes on setting to conform to CAN Segment name Settable range...
Page 551 CAN Controller (CAN) Chapter 18 Synchronizing data bit • The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. • The transmitting node transmits data in synchronization with the bit timing of the transmitting node.
Page 552: Connection With Target System
Chapter 18 CAN Controller (CAN) If phase error is positive CAN bus Prop Sync Phase Bit timing Phase segment 1 segment segment segment 2 Sample point If phase error is negative CAN bus Prop Phase Sync Bit timing Phase segment 1 segment segment 2 segment...
Page 553: Internal Registers Of Can Controller
CAN Controller (CAN) Chapter 18 18.5 Internal Registers of CAN Controller 18.5.1 CAN module register and message buffer addresses In this chapter all register and message buffer addresses are defined as address offsets to different base addresses. Since all registers are accessed via the programmable peripheral area the bottom address is defined by the BPC register (refer to “Programmable peripheral I/O area”...
Page 554: Can Controller Configuration
Chapter 18 CAN Controller (CAN) 18.5.2 CAN Controller configuration Table 18-18 List of CAN Controller registers Item Register Name CAN global registers CANn global control register (CnGMCTRL) CANn global clock selection register (CnGMCS) CANn global automatic block transmission control register (CnGMABT) CANn global automatic block transmission delay setting register (CnGMABTD) CAN module registers CANn module mask 1 register (CnMASK1L, CnMASK1H)
Page 555: Can Registers Overview
CAN Controller (CAN) Chapter 18 18.5.3 CAN registers overview CAN0 module registers The following table lists the address offsets to the CAN0 register base address: C0RBaseAddr = PBA Table 18-19 CAN0 global and module registers Access Address Register name Symbol After reset offset 1-bit...
Page 556 Chapter 18 CAN Controller (CAN) The addresses in the following table denote the address offsets to the CAN #n message buffer base address: CnMBaseAddr, with m being the message buffer number. Example CAN0, message buffer m = 14 = E , byte 6 C0MDATA614 has the address E x 20 + C0MBaseAddr...
Page 557: Register Bit Configuration
CAN Controller (CAN) Chapter 18 18.5.4 Register bit configuration Table 18-21 CAN global register bit configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 offset CnGMCTRL (W) Clear GOM Set EFSD Set GOM CnGMCTRL (R) EFSD...
Page 558 Chapter 18 CAN Controller (CAN) Table 18-22 CAN module register bit configuration (2/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 offset CnLEC (W) CnLEC (R) LEC2 LEC1 LEC0 CnINFO BOFF TECS1 TECS0...
Page 559 CAN Controller (CAN) Chapter 18 Table 18-23 Message buffer register bit configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 offset CnMDATA01m Message data (byte 0) Message data (byte 1) CnMDATA0m Message data (byte 0) CnMDATA1m...
Page 560: Bit Set/Clear Function
Chapter 18 CAN Controller (CAN) 18.6 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.
Page 561 CAN Controller (CAN) Chapter 18 Register’s current value Write value clear 1 Register’s value after write operation Figure 18-23 Example of bit setting/clearing operations Bit status after bit setting/clearing operations Clear Clear Clear Clear Clear Clear Clear Clear Set 7 Set 6 Set 5 Set 4...
Page 562: Control Registers
Chapter 18 CAN Controller (CAN) 18.7 Control Registers CnGMCTRL - CANn global control register The CnGMCTRL register is used to control the operation of the CAN module. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 000 Initial Value 0000 .
Page 563 CAN Controller (CAN) Chapter 18 Caution To request forced shut down, the GOM bit must be cleared to 0 in a subsequent, immediately following access after the EFSD bit has been set to 1. If access to another register (including reading the CnGMCTRL register) is executed without clearing the GOM bit immediately after the EFSD bit has been set to 1, the EFSD bit is forcibly cleared to 0, and the forced shut down request is invalid.
Page 564 Chapter 18 CAN Controller (CAN) CnGMCS - CANn global clock selection register The CnGMCS register is used to select the CAN module system clock. Access This register can be read/written in 8-bit units. Address <CnRBaseAddr> + 002 Initial Value . The register is initialized by any reset. CCP3 CCP2 CCP1...
Page 565 CAN Controller (CAN) Chapter 18 CnGMABT - CANn global automatic block transmission control register The CnGMABT register is used to control the automatic block transmission (ABT) operation. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 006 Initial Value 0000 .
Page 566 Chapter 18 CAN Controller (CAN) (b) CnGMABT write ABTCLR ABTTRG Clear ABTTRG Caution Before changing the normal operation mode with ABT to the initialization mode, be sure to set the CnGMABT register to the default value (0000 ) and confirm the CnGMABT register is surely initialized to the default value (0000 Set ABTCLR Automatic block transmission engine clear request bit The automatic block transmission engine is in idle status or under...
Page 567 CAN Controller (CAN) Chapter 18 CnGMABTD - CANn global automatic block transmission delay register The CnGMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT.
Page 568 Chapter 18 CAN Controller (CAN) CnMASKaL, CnMASKaH - CANn module mask control register (a = 1 to 4) The CnMASKaL and CnMASKaH registers are used to extend the number of receivable messages into the same message buffer by masking part of the identifier (ID) comparison of a message and invalidating the ID of the masked part.
Page 569 CAN Controller (CAN) Chapter 18 (c) CANn module mask 3 register (CnMASK3L, CnMASK3H) Access These registers can be read/written in 16-bit units. Address CnMASK3L: <CnRBaseAddr> + 048 CnMASK3H: <CnRBaseAddr> + 04A Initial Value Undefined. CnMASK3L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8...
Page 570 Chapter 18 CAN Controller (CAN) CnCTRL - CANn module control register The CnCTRL register is used to control the operation mode of the CAN module. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 050 Initial Value 0000 .
Page 571 CAN Controller (CAN) Chapter 18 CCERC Error counter clear bit The CnERC and CnINFO registers are not cleared in the initialization mode. The CnERC and CnINFO registers are cleared in the initialization mode. Note The CCERC bit is used to clear the CnERC and CnINFO registers for re-initialization or forced recovery from the bus-off state.
Page 572 Chapter 18 CAN Controller (CAN) PSMODE1 PSMODE0 Power save mode No power save mode is selected. CAN sleep mode Setting prohibited CAN stop mode Caution Transition to and from the CAN stop mode must be made via CAN sleep mode. A request for direct transition to and from the CAN stop mode is ignored.
Page 573 CAN Controller (CAN) Chapter 18 (b) CnCTRL write CCERC PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0 Clear Clear Clear Clear Clear Clear Clear VALID PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0 Set CCERC Setting of CCERC bit CCERC bit is set to 1. Other than above CCERC bit is not changed.
Page 574 Chapter 18 CAN Controller (CAN) Clear Setting of OPMODE1 bit OPMODE1 OPMODE1 OPMODE1 bit is cleared to 0. OPMODE1 bit is set to 1. Other than above OPMODE1 bit is not changed. Clear Setting of OPMODE2 bit OPMODE2 OPMODE2 OPMODE2 bit is cleared to 0. OPMODE2 bit is set to 1.
Page 575 CAN Controller (CAN) Chapter 18 CnINFO - CANn module information register The CnINFO register indicates the status of the CAN module. Access This register is read-only in 8-bit units. Address <CnRBaseAddr> + 053 Initial Value . The register is initialized by any reset. BOFF TECS1 TECS0...
Page 576 Chapter 18 CAN Controller (CAN) CnERC - CANn module error counter register The CnERC register indicates the count value of the transmission/reception error counter. Access This register is read-only in 16-bit units. Address <CnRBaseAddr> + 054 Initial Value 0000 . The register is initialized by any reset. REPS REC6 REC5...
Page 577 CAN Controller (CAN) Chapter 18 (10) CnIE - CANn module interrupt enable register The CnIE register is used to enable or disable the interrupts of the CAN module. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 056 Initial Value 0000 .
Page 578 Chapter 18 CAN Controller (CAN) Set CIE2 Clear CIE2 Setting of CIE2 bit CIE2 bit is cleared to 0. CIE2 bit is set to 1. Other than above CIE2 bit is not changed. Set CIE1 Clear CIE1 Setting of CIE1 bit CIE1 bit is cleared to 0.
Page 579 CAN Controller (CAN) Chapter 18 (11) CnINTS - CANn module interrupt status register The CnINTS register indicates the interrupt status of the CAN module. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 058 Initial Value 0000 .
Page 580 Chapter 18 CAN Controller (CAN) (12) CnBRP - CANn module bit rate prescaler register The CnBRP register is used to select the CAN protocol layer basic system clock (f ). The communication baud rate is set to the CnBTR register. Access This register can be read/written in 8-bit units.
Page 581 CAN Controller (CAN) Chapter 18 (13) CnBTR - CANn module bit rate register The CnBTR register is used to control the data bit time of the communication baud rate. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 05C Initial Value 370F .
Page 582 Chapter 18 CAN Controller (CAN) TSEG13 TSEG12 TSEG11 TSEG10 Length of time segment 1 Setting prohibited (default value) This setting must not be made when the CnBRP register = 00 Note = 1/f : CAN protocol layer basic system clock) (14) CnLIPT - CANn module last in-pointer register The CnLIPT register indicates the number of the message buffer in which a...
Page 583 CAN Controller (CAN) Chapter 18 (15) CnRGPT - CANn module receive history list register The CnRGPT register is used to read the receive history list. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 060 Initial Value xx02 .
Page 584 Chapter 18 CAN Controller (CAN) (b) CnRGPT write Clear ROVF Clear ROVF Setting of ROVF bit ROVF bit is not changed. ROVF bit is cleared to 0. (16) CnLOPT - CANn module last out-pointer register The CnLOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last.
Page 585 CAN Controller (CAN) Chapter 18 (17) CnTGPT - CANn module transmit history list register The CnTGPT register is used to read the transmit history list. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 064 Initial Value xx02 .
Page 586 Chapter 18 CAN Controller (CAN) (b) CnTGPT write Clear TOVF Clear Setting of TOVF bit TOVF TOVF bit is not changed. TOVF bit is cleared to 0. User’s Manual U18743EE1V2UM00...
Page 587 CAN Controller (CAN) Chapter 18 (18) CnTS - CANn module time stamp register The CnTS register is used to control the time stamp function. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 066 Initial Value 0000 .
Page 588 Chapter 18 CAN Controller (CAN) (b) CnTS write TSLOCK TSSEL TSEN Clear Clear Clear TSLOCK TSSEL TSEN Clear Setting of TSLOCK bit TSLOCK TSLOCK TSLOCK bit is cleared to 0. TSLOCK bit is set to 1. Other than above TSLOCK bit is not changed. Clear Setting of TSSEL bit TSSEL...
Page 589 CAN Controller (CAN) Chapter 18 (19) CnMDATAxm, CnMDATAzm - CANn message data byte register (x = 0 to 7, z = 01, 23, 45, 67) The CnMDATAxm, CnMDATAzm registers are used to store the data of a transmit/receive message. Access The CnMDATAzm registers can be read/written in 16-bit units.
Page 590 Chapter 18 CAN Controller (CAN) CnMDATA45m MDATA4515 MDATA4514 MDATA4513 MDATA4512 MDATA4511 MDATA4510 MDATA459 MDATA458 MDATA457 MDATA456 MDATA455 MDATA454 MDATA453 MDATA452 MDATA451 MDATA450 CnMDATA4m MDATA47 MDATA46 MDATA45 MDATA44 MDATA43 MDATA42 MDATA41 MDATA40 CnMDATA5m MDATA57 MDATA56 MDATA55 MDATA54 MDATA53 MDATA52 MDATA51 MDATA50 CnMDATA67m MDATA6715 MDATA6714 MDATA6713 MDATA6712 MDATA6711 MDATA6710 MDATA679...
Page 591 CAN Controller (CAN) Chapter 18 (20) CnMDLCm - CANn message data length register m The CnMDLCm register is used to set the number of bytes of the data field of a message buffer. Access This register can be read/written in 8-bit units. Address Refer to “CAN registers overview”...
Page 592 Chapter 18 CAN Controller (CAN) (21) CnMCONFm - CANn message configuration register m The CnMCONFm register is used to specify the type of the message buffer and to set a mask. Access This register can be read/written in 8-bit units. Address Refer to “CAN registers overview”...
Page 593 CAN Controller (CAN) Chapter 18 Message buffer assignment bit Message buffer not used. Message buffer used. Caution Be sure to write 0 to bits 2 and 1. User’s Manual U18743EE1V2UM00...
Page 594 Chapter 18 CAN Controller (CAN) (22) CnMIDLm, CnMIDHm - CANn message ID register m The CnMIDLm and CnMIDHm registers are used to set an identifier (ID). Access These registers can be read/written in 16-bit units. Address Refer to “CAN registers overview” on page 555. Initial Value Undefined.
Page 595 CAN Controller (CAN) Chapter 18 (23) CnMCTRLm - CANn message control register m The CnMCTRLm register is used to control the operation of the message buffer. Access This register can be read/written in 16-bit units. Address Refer to “CAN registers overview” on page 555. Initial Value 00x0 0000 0000 0000 .
Page 596 Chapter 18 CAN Controller (CAN) Message buffer transmission request bit No message frame transmitting request that is pending or being transmitted is in the message buffer. The message buffer is holding transmission of a message frame pending or is transmitting a message frame. Message buffer ready bit The message buffer can be written by software.
Page 597 CAN Controller (CAN) Chapter 18 Set RDY Clear RDY Setting of RDY bit RDY bit is cleared to 0. RDY bit is set to 1. Other than above RDY bit is not changed. Caution Set IE bit and RDY bit always separately. Do not set the DN bit to 1 by software.
Page 598: Can Controller Initialization
Chapter 18 CAN Controller (CAN) 18.8 CAN Controller Initialization 18.8.1 Initialization of CAN module Before CAN module operation is enabled, the CAN module system clock needs to be determined by setting the CCP[3:0] bits of the CnGMCS register by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled.
Page 599 CAN Controller (CAN) Chapter 18 the transmit message buffer, set a transmission request using the procedure described below. When setting a transmission request to a message buffer that has been redefined without aborting the transmission in progress, however, the 1-bit wait time is not necessary. Redefinition completed Execute transmission?
Page 600: Transition From Initialization Mode To Operation Mode
Chapter 18 CAN Controller (CAN) 18.8.4 Transition from initialization mode to operation mode The CAN module can be switched to the following operation modes. • Normal operation mode • Normal operation mode with ABT • Receive-only mode • Single-shot mode •...
Page 601: Resetting Error Counter Cnerc Of Can Module
CAN Controller (CAN) Chapter 18 18.8.5 Resetting error counter CnERC of CAN module If it is necessary to reset the CAN module error counter CnERC and CAN module information register CnINFO when re-initialization or forced recovery from the bus-off status is made, set the CCERC bit of the CnCTRL register to 1 in the initialization mode.
Page 602: Message Reception
Chapter 18 CAN Controller (CAN) 18.9 Message Reception 18.9.1 Message reception In all the operation modes, the complete message buffer area is analyzed to find a suitable buffer to store a newly received message. All message buffers satisfying the following conditions are included in that evaluation (RX-search process).
Page 603: Receive Data Read
CAN Controller (CAN) Chapter 18 18.9.2 Receive data read To keep data consistency when reading CAN message buffers, perform the data reading according to Figure 18-49 on page 651 to Figure 18-51 on page 653. During message reception, the CAN module sets DN of the CnMCTRLm register two times: at the beginning of the storage process of data to the message buffer, and again at the end of this storage process.
Page 604: Receive History List Function
Chapter 18 CAN Controller (CAN) 18.9.3 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding CnLIPT register and the receive history list get pointer (RGPT) with the corresponding CnRGPT register.
Page 605 CAN Controller (CAN) Chapter 18 As long as the RHL contains 23 or less entries the sequence of occurrence is maintained. If more receptions occur without reading the RHL by the host processor, complete sequence of receptions can not be recovered. Figure 18-29 Receive history list User’s Manual U18743EE1V2UM00...
Page 606: Mask Function
Chapter 18 CAN Controller (CAN) 18.9.4 Mask function For any message buffer, which is used for reception, the assignment to one of four global reception masks (or no mask) can be selected. By using the mask function, the message ID comparison can be reduced by masked bits, herewith allowing the reception of several different IDs into one buffer.
Page 607 CAN Controller (CAN) Chapter 18 The CMID27 to CMID24 and CMID22 bits are cleared to 0, and the CMID28, CMID23, and CMID21 to CMID0 bits are set to 1. User’s Manual U18743EE1V2UM00...
Page 608: Multi Buffer Receive Block Function
Chapter 18 CAN Controller (CAN) 18.9.5 Multi buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type.
Page 609: Remote Frame Reception
CAN Controller (CAN) Chapter 18 18.9.6 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. •...
Page 610: Message Transmission
Chapter 18 CAN Controller (CAN) 18.10 Message Transmission 18.10.1 Message transmission A message buffer with its TRQ bit set to 1 participates in the search for the most high-prioritized message when the following conditions are fulfilled. This behavior is valid for all operational modes. •...
Page 611 CAN Controller (CAN) Chapter 18 Priority Conditions Description 1 (high) Value of first 11 bits of ID The message frame with the lowest value represented by the first 11 [ID28 to ID18]: bits of the ID is transmitted first. If the value of an 11-bit standard ID is equal to or smaller than the first 11 bits of a 29-bit extended ID, the 11-bit standard ID has a higher priority than a message frame with a 29-bit extended ID.
Page 612: Transmit History List Function
Chapter 18 CAN Controller (CAN) 18.10.2 Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer from which data or remote frames have been were sent. The THL consists of storage elements equivalent to up to seven messages, the last out-message pointer (LOPT) with the corresponding CnLOPT register, and the transmit history list get pointer (TGPT) with the corresponding CnTGPT register.
Page 613 CAN Controller (CAN) Chapter 18 Caution If the history list is in the overflow condition (TOVF is set), reading the history list contents is still possible, until the history list is empty (indicated by THPM flag set). Nevertheless, the history list remains in the overflow condition, until TOVF is cleared by software.
Page 614: Automatic Block Transmission (Abt)
Chapter 18 CAN Controller (CAN) 18.10.3 Automatic block transmission (ABT) The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message buffer numbers 0 to 7).
Page 615 CAN Controller (CAN) Chapter 18 held pending and the transmission ID of the message buffers other than those used by the ABT function. Transmission of a data frame from an ABT message buffer is not recorded in the transmit history list (THL). Caution Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0 in order to resume ABT operation at buffer No.0.
Page 616: Transmission Abort Process
Chapter 18 CAN Controller (CAN) 18.10.4 Transmission abort process Transmission abort process except for in normal operation mode with automatic block transmission (ABT) The user can clear the TRQ bit of the CnMCTRLm register to 0 to abort a transmission request. The TRQ bit will be cleared immediately if the abort was successful.
Page 617: Remote Frame Transmission
CAN Controller (CAN) Chapter 18 Status of TRQ of Abort after successful transmission Abort after erroneous transmission ABT message buffer Set (1) Next message buffer in the ABT area Same message buffer in the ABT area Cleared (0) Next message buffer in the ABT area Next message buffer in the ABT area The above resumption operation can be performed only if a message buffer ready for ABT exists in the ABT area.
Page 618: Power Saving Modes
Chapter 18 CAN Controller (CAN) 18.11 Power Saving Modes 18.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN Controller to stand-by mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes.
Page 619 CAN Controller (CAN) Chapter 18 the operation modes, immediate transition to the CAN sleep mode is not possible. In this case, the CAN sleep mode transition request has to be held pending until the CAN bus state becomes bus idle (the 4th bit in the interframe space is recessive).
Page 620 Chapter 18 CAN Controller (CAN) Releasing CAN sleep mode The CAN sleep mode is released by the following events: • When the CPU writes 00 to the PSMODE[1:0] bits of the CnCTRL register • A falling edge at the CAN reception pin (CRXDn) (i.e. the CAN bus level shifts from recessive to dominant) Caution Even if the falling edge belongs to the SOF of a receive message, this...
Page 621: Can Stop Mode
CAN Controller (CAN) Chapter 18 18.11.2 CAN stop mode The CAN stop mode can be used to set the CAN Controller to stand-by mode to reduce power consumption. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the CAN module in the CAN sleep mode.
Page 622: Example Of Using Power Saving Modes
Chapter 18 CAN Controller (CAN) 18.11.3 Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus.
Page 623: Interrupt Function
CAN Controller (CAN) Chapter 18 18.12 Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register.
Page 624: Diagnosis Functions And Special Operational Modes
Chapter 18 CAN Controller (CAN) 18.13 Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis functions or the operation of special CAN communication methods. 18.13.1 Receive-only mode The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and can be used for CAN bus analysis nodes.
Page 625: Single-Shot Mode
CAN Controller (CAN) Chapter 18 Furthermore, in the receive-only mode ACK is not returned to the CAN bus in this mode upon the valid reception of a message frame. Internally, the local node recognizes that it has transmitted ACK. An overload frame cannot be transmitted to the CAN bus.
Page 626: Self-Test Mode
Chapter 18 CAN Controller (CAN) The single-shot mode can be used when emulating time-triggered communication methods (e.g., TTCAN level 1). Caution The AL bit is only valid in single-shot mode. It does not influence the operation of re-transmission upon arbitration loss in the other operation modes. 18.13.3 Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or...
Page 627: Receive/Transmit Operation In Each Operation Mode
CAN Controller (CAN) Chapter 18 18.13.4 Receive/transmit operation in each operation mode The following table shows outline of the receive/transmit operation in each operation mode. Table 18-26 Outline of the receive/transmit in each operation mode Transmis- Transmis- Automatic sion of Transmis- sion of Store data to...
Page 628: Time Stamp Function
Chapter 18 CAN Controller (CAN) 18.14 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may have different frequencies).
Page 629: Baud Rate Settings
CAN Controller (CAN) Chapter 18 Caution The time stamp function using the TSLOCK bit stops toggle of the TSOUT signal by receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer. Since a receive message buffer cannot receive a remote frame, toggle of the TSOUT signal cannot be stopped by reception of a remote frame.
Page 630 Chapter 18 CAN Controller (CAN) Table 18-27 shows the combinations of bit rates that satisfy the above conditions. Table 18-27 Settable bit rate combinations (1/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG1 TSEG2 (unit %) DBT length...
Page 631 CAN Controller (CAN) Chapter 18 Table 18-27 Settable bit rate combinations (2/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG1 TSEG2 (unit %) DBT length SEGMENT SEGMENT SEGMENT1 SEGMENT2 [3:0] [2:0] 1001 64.7 1010 70.6 1011...
Page 632 Chapter 18 CAN Controller (CAN) Table 18-27 Settable bit rate combinations (3/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG1 TSEG2 (unit %) DBT length SEGMENT SEGMENT SEGMENT1 SEGMENT2 [3:0] [2:0] 1000 83.3 1001 91.7 0101...
Page 633: Representative Examples Of Baud Rate Settings
CAN Controller (CAN) Chapter 18 18.15.2 Representative examples of baud rate settings Table 18-28 and Table 18-29 show representative examples of baud rate settings. Table 18-28 Representative examples of baud rate settings = 8 MHz) (1/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud...
Page 634 Chapter 18 CAN Controller (CAN) Table 18-28 Representative examples of baud rate settings = 8 MHz) (2/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC...
Page 635 CAN Controller (CAN) Chapter 18 Table 18-29 Representative examples of baud rate settings = 16 MHz) (1/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC...
Page 636 Chapter 18 CAN Controller (CAN) Table 18-29 Representative examples of baud rate settings = 16 MHz) (2/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC...
Page 637: Operation Of Can Controller
CAN Controller (CAN) Chapter 18 18.16 Operation of CAN Controller The processing procedure for showing in this chapter is recommended processing procedure to operate CAN controller. Develop the program referring to recommended processing procedure in this chapter. START CnGMCS register. CnGMCTRL register (set GOM bit = 1) CnBRP register,...
Page 638 Chapter 18 CAN Controller (CAN) START START Clear Clear OPMODE OPMODE INIT mode? INIT mode? CnBRP register, CnBRP register, CnBTR register CnBTR register CnIE register CnIE register CnMASK register CnMASK register Initialize message buffers Initialize message buffers CnERC and CnINFO CnERC and CnINFO register clear? register clear?
Page 639 CAN Controller (CAN) Chapter 18 START START RDY = 1? RDY = 1? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? CnMCONFm register CnMCONFm register CnMIDHm register, CnMIDHm register, CnMIDLm register CnMIDLm register Transmit message buffer? Transmit message buffer? CnMDLCm register CnMDLCm register...
Page 640 Chapter 18 CAN Controller (CAN) Figure 18-38 shows the processing for a receive message buffer (MT[2:0] bits of CnMCONFm register = 001 to 101 START Clear VALID bit RDY = 1? Clear RDY bit RDY = 0? RSTAT = 0 or VALID = 1? Note1 Note2...
Page 641 CAN Controller (CAN) Chapter 18 Figure 18-39 shows the processing for a transmit message buffer during transmission (MT[2:0] bits of CnMCONFm register = 000 START START Transmit abort process Transmit abort process Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Data frame Data frame...
Page 642 Chapter 18 CAN Controller (CAN) Figure 18-40 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000 START START TRQ = 0? TRQ = 0? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Data frame Data frame Remote frame...
Page 643 CAN Controller (CAN) Chapter 18 Figure 18-41 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000 START START ABTTRG = 0? ABTTRG = 0? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Set CnMDATAxm register Set CnMDATAxm register Set CnMDLCm register...
Page 644 Chapter 18 CAN Controller (CAN) START START Transmit completion Transmit completion Transmit completion interrupt processing interrupt processing interrupt processing Read CnLOPT register Read CnLOPT register Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Data frame Data frame Remote frame Remote frame Data frame or remote frame?
Page 645 CAN Controller (CAN) Chapter 18 START START Transmit completion Transmit completion Transmit completion interrupt processing interrupt processing interrupt processing Read CnTGPT register Read CnTGPT register TOVF = 1? TOVF = 1? Clear TOVF bit Clear TOVF bit Clear RDY bit Clear RDY bit RDY = 0? RDY = 0?
Page 646 Chapter 18 CAN Controller (CAN) the processing have to be discarded and processed again, after MBON is set again. It is recommended to cancel any sleep mode requests, before processing TX interrupts. If TOVF was set once, the transmit history list is inconsistent. Consider to scan all configured transmit buffers for completed transmissions.
Page 647 CAN Controller (CAN) Chapter 18 Note Also check the MBON flag at the beginning and at the end of the polling routine, in order to check the access to the message buffers as well as TX history list registers, in case a pending sleep mode had been executed. If MBON is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after MBON is set again.
Page 648 Chapter 18 CAN Controller (CAN) START START Clear ABTTRG bit Clear ABTTRG bit ABTTRG = 0? ABTTRG = 0? Clear TRQ bit Clear TRQ bit Wait for 11 CAN data bits Wait for 11 CAN data bits TSTAT = 0? TSTAT = 0? Read CnLOPT register Read CnLOPT register...
Page 649 CAN Controller (CAN) Chapter 18 Figure 18-47 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. START START TSTAT = 0? TSTAT = 0? Clear ABTTRG bit Clear ABTTRG bit ABTTRG = 0? ABTTRG = 0?
Page 650 Chapter 18 CAN Controller (CAN) Figure 18-48 shows the processing to not skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. START START Clear TRQ bit of message buffer Clear TRQ bit of message buffer undergoing transmission undergoing transmission Clear ABTTRG bit...
Page 651 CAN Controller (CAN) Chapter 18 START START Generation of receive Generation of receive completion interrupt completion interrupt Read CnLIPT register Read CnLIPT register Clear DN bit Clear DN bit Read CnMDATAxm, CnMDLCm, Read CnMDATAxm, CnMDLCm, CnMIDLm, and CnMIDHm CnMIDLm, and CnMIDHm registers registers DN = 0...
Page 652 Chapter 18 CAN Controller (CAN) START START Generation of receive Generation of receive completion interrupt completion interrupt Read CnRGPT register Read CnRGPT register ROVF = 1? ROVF = 1? Clear ROVF bit Clear ROVF bit RHPM = 1? RHPM = 1? Clear DN bit Clear DN bit Read CnMDATAxm, CnMDLCm,...
Page 653 CAN Controller (CAN) Chapter 18 START START CINTS1 = 1? CINTS1 = 1? Clear CINTS1 bit Clear CINTS1 bit Read CnRGPT register Read CnRGPT register ROVF = 1? ROVF = 1? Clear ROVF bit Clear ROVF bit RHPM = 1? Clear DN bit Clear DN bit Read CnMDATAxm, CnMDLCm,...
Page 654 Chapter 18 CAN Controller (CAN) START (when PSMODE[1:0] = 00B) START (when PSMODE[1:0] = 00B) Set PSMODE0 bit Set PSMODE0 bit PSMODE0 = 1? PSMODE0 = 1? CAN sleep mode CAN sleep mode CAN sleep mode Set PSMODE1 bit Set PSMODE1 bit PSMODE1 = 1? PSMODE1 = 1? Request CAN sleep...
Page 655 CAN Controller (CAN) Chapter 18 START CAN stop mode Clear PSMODE1 bit CAN sleep mode Releasing CAN sleep mode by CAN bus activity Releasing CAN sleep mode by user Dominant edge on CAN detected Clear PSMODE0 bit Clear PSMODE0 bit Clear PSMODE0 bit Clear CINTS5 bit Figure 18-53...
Page 656 Chapter 18 CAN Controller (CAN) START BOFF = 1? Note Clear all TRQ bits Set CnCTRL register (Clear OPMODE) Access to registers other than CnCTRL and CnGMCTRL registers Forced recovery from bus off? Set CnCTRL register Set CCERC bit (Set OPMODE) Set CnCTRL register Wait for recovery (Set OPMODE)
Page 657 CAN Controller (CAN) Chapter 18 START BOFF = 1? Clear ABTTRG bit Note Clear all TRQ bits Set CnCTRL register (Clear OPMODE) Access to registers other than CnCTRL and CnGMCTRL registers Forced recovery from bus off? Set CnCTRL register Set CnCTRL register Set CCERC bit (Set OPMODE) (Set OPMODE)
Page 658 Chapter 18 CAN Controller (CAN) START START INIT mode Clear GOM bit GOM = 0? Shutdown successful GOM = 0, EFSD = 0 Figure 18-56 Normal shutdown process User’s Manual U18743EE1V2UM00...
Page 659 CAN Controller (CAN) Chapter 18 START Set EFSD bit Must be a subsequent write Clear GOM bit Clear GOM bit GOM = 0? GOM = 0? Shutdown successful GOM = 0, EFSD = 0 Figure 18-57 Forced shutdown process Caution Do not read- or write-access any registers by software between setting the EFSD bit and clearing the GOM bit.
Page 660 Chapter 18 CAN Controller (CAN) START Error interrupt CINTS2 = 1? Check CAN module state (read CnINFO register) Clear CINTS2 bit CINTS3 = 1? CINTS3 = 1? Check CAN protocol error state (read CnLEC register) Clear CINTS3 bit CINTS4 = 1? Clear CINTS4 bit Figure 18-58 Error handling...
Page 661 CAN Controller (CAN) Chapter 18 START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? Clear CINTS5 bit. Clear CINTS5 bit = 1 CAN sleep mode CINTS5 bit = 1? MBON bit = 0? Set CPU standby mode.
Page 662 Chapter 18 CAN Controller (CAN) START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? Clear CINTS5 bit. Clear CINTS5 bit = 1 CAN sleep mode Set PSMODE1 bit. Set PSMODE1 bit = 1 Clear PSMODE1 bit = 0 PSMODE1 bit = 1? CAN stop mode...
Page 663: Chapter 19 A/D Converter (Adc)
Chapter 19 A/D Converter (ADC) The V850ES/Fx3-L microcontrollers have following instances of the A/D Converter ADC: V850ES/FE3-L V850ES/FF3-L V850ES/FG3-L Instances Names ADA0 ADA0 ADA0 Channels Throughout this chapter, the individual instances of ADC are identified by “n”, for example, ADAnM0 for the ADAn mode register 0. Throughout this chapter, the individual channels of each ADC instance are identified by “m”, for example, ADAnCRm for the conversion result register m of ADAn.
Page 664 Chapter 19 A/D Converter (ADC) The block diagram of the A/D Converter is shown below. REF0 ADAnPS bit Sample & hold circuit ANI0 ANI1 ADC0 ANIm ADAnCE bit V olt age comp arator INTAD ADAnPFE bit Control ADAnPFC bit Circuit INTTAA2CC0 INTTAA2CC1 ADAnCR0...
Page 665: Configuration
A/D Converter (ADC) Chapter 19 19.2 Configuration The A/D Converter includes the following hardware. Table 19-1 Configuration of A/D Converter Item Configuration Analog inputs ANI0 to ANIm Registers Successive approximation register (SAR) A/D conversion result registers ADAnCRm, ADAnCRmH AVREF A/D conversion diagnostic registers ADAnCRDD, ADAnCRDDH AVSS A/D conversion diagnostic registers ADAnCRSS, ADAnCRSSH ADC power-fail compare mode register ADAnPFM ADC power-fail compare threshold value register ADAnPFT...
Page 666 Chapter 19 A/D Converter (ADC) Sample & hold circuit The sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the sampled data to the Voltage Comparator. This circuit also holds the sampled analog input signal voltage during A/D conversion.
Page 667: Adc Registers
A/D Converter (ADC) Chapter 19 19.3 ADC Registers The A/D Converter is controlled by the following registers: • A/D Converter mode registers 0, 1, 2 (ADAnM0, ADAnM1, ADAnM2) • A/D Converter channel specification register 0 (ADAnS) • Power-fail compare mode register (ADAnPFM) The following registers are also used: •...
Page 668 Chapter 19 A/D Converter (ADC) Specification of external trigger (ADTRG pin) input ADAnETS1 ADAnETS0 valid edge No edge detection Falling edge detection Rising edge detection Detection of both rising and falling edges ADAnTMD Trigger mode specification Software trigger mode External trigger mode/ timer trigger mode ADAnEF A/D Converter status display A/D conversion stopped...
Page 669 A/D Converter (ADC) Chapter 19 ADAnM1 - ADC mode register 1 The ADAnM1 register is an 8-bit register that controls the conversion time specification. This register can be read or written in 8-bit or 1-bit units. Reset input clears this bit to 00H. After reset: 00H Address: ADA0M1 FFFFF201H...
Page 670 Chapter 19 A/D Converter (ADC) Table 19-3 Conversion time settings (2/2) 64/f 3.20 µs 4.00 µs 6.40 µs 16.00 µs 96/f 4.80 µs 6.00 µs 9.60 µs prohibited 128/f 6.40 µs 8.00 µs 12.80 µs prohibited 160/f 8.00 µs 10.00 µs 16.00 µs prohibited 192/f...
Page 671 A/D Converter (ADC) Chapter 19 ADAnM2 - ADC mode register 2 The ADAnM2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: AD0M2 FFFFF203H ADAnM2...
Page 672 Chapter 19 A/D Converter (ADC) ADAnS - ADC channel specification register The ADAnS register specifies the pin that inputs the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 673 A/D Converter (ADC) Chapter 19 Analog input to convert ADAnS[4:0] ADAnDIAG = 0 ADAnDIAG = 1 (without diagnostic function) (with diagnostic function) Select Select Scan mode Scan mode mode mode ANI16 ANI0 to ANI16 prohibited ANI0 to ANI16 - AVREF - AVSS ANI17 ANI0 to ANI17...
Page 674 Chapter 19 A/D Converter (ADC) ADAnCRm, ADAnCRmH - ADC conversion result registers The ADAnCRm and ADAnCRmH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, specify the ADAnCRm register for 16-bit access and the ADAnCRmH register for 8-bit access.
Page 675 A/D Converter (ADC) Chapter 19 The relationship between the analog voltage input to the analog input pins ANInmm and the A/D conversion result (of A/D conversion result register n ADAnCRm is as follows: • ----------------- - 1024 ADnCRm • ≤ <...
Page 676 Chapter 19 A/D Converter (ADC) ADAnCRDD, ADAnCRDDH - AVREF A/D conversion diagnostic registers The ADAnCRDD and ADAnCRDDH registers store the result of the AVREF conversion if the ADC diagnostic function is enabled (ADAnM2.ADAnDIAG = 1). These registers are read-only, in 16-bit or 8-bit units. However, specify the ADAnCRDD register for 16-bit access and the ADAnCRDDH register for 8-bit access.
Page 677 A/D Converter (ADC) Chapter 19 ADAnCRSS, ADAnCRSSH - AVSS A/D conversion diagnostic registers The ADAnCRSS and ADAnCRSSH registers store the result of the AVSS conversion if the ADC diagnostic function is enabled (ADAnM2.ADAnDIAG = 1). These registers are read-only, in 16-bit or 8-bit units. However, specify the ADAnCRSS register for 16-bit access and the ADAnCRSSH register for 8-bit access.
Page 678 Chapter 19 A/D Converter (ADC) ADAnPFM - ADC power-fail compare mode register The ADAnPFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: ADA0PFM FFFFF204H...
Page 679 A/D Converter (ADC) Chapter 19 ADAnPFT - ADC power-fail compare threshold value register The ADAnPFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: ADA0PFT FFFFF205H...
Page 680: Operation
Chapter 19 A/D Converter (ADC) 19.4 Operation 19.4.1 Basic operation 1. Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADAnM0, ADAnM1, ADAnM2, and ADAnS registers. Set the ADAnPS bit of the ADAnM0 register to supply power to the analog circuitry of the ADC.
Page 681: Trigger Mode
A/D Converter (ADC) Chapter 19 Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined resul t Conversion ADAnCRm resul t INTAD INTAD1 Figure 19-3 A/D Converter basic operation 19.4.2 Trigger mode The timing of starting the conversion operation is specified by setting a trigger mode.
Page 682 Chapter 19 A/D Converter (ADC) External trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI23) specified by the ADAnS register is started when an external trigger is input (to the ADTRG pin). Which edge of the external trigger is to be detected (i.e., the rising edge, falling edge, or both rising and falling edges) can be specified by using the ADAnETS1 and ADAnETS0 bits of the ADAnM0 register.
Page 683: Operation Modes
A/D Converter (ADC) Chapter 19 19.4.3 Operation modes Four operation modes are available as the modes in which to set the ANInmm pins: continuous select mode, continuous scan mode, one-shot select mode and one-shot scan mode.. The operation mode is selected by the ADAnMD1 and ADAnMD0 bits of the ADAnM0 register.
Page 684 Chapter 19 A/D Converter (ADC) (a) Timing example ANI0 Data 1 Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 conversion ANI0) (ANI1) (ANI2) (ANI3) (ANI0) ANI1) (ANI2) Data 1...
Page 685 A/D Converter (ADC) Chapter 19 One-shot select mode In this mode, the voltage on the analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis.
Page 686 Chapter 19 A/D Converter (ADC) One-shot scan mode In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADAnS register, and their values are converted into digital values. The result of each conversion is stored in the ADAnCRm register corresponding to the analog input pin.
Page 687 A/D Converter (ADC) Chapter 19 Diagnostic mode When activating the diagnostic mode (ADADIAG bit of ADAnM2 register is set) the voltage at the AVREF pin and the AVSS pin are sampled after conversion of the specified ANInm range is finished. The resulting values can be found in the ADAnCRDD, ADAnCRDDH, ADAnCRSS and ADAnCRSSH registers.
Page 688: Power-Fail Compare Mode
Chapter 19 A/D Converter (ADC) 19.4.4 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADAnPFM and ADAnPFT registers. • When the ADAnPFE bit = 0, the INTAD signal is generated each time conversion is completed (normal use of the A/D Converter).
Page 689 A/D Converter (ADC) Chapter 19 Continuous scan mode In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin to the pin specified by the ADAnS register are stored, and the set value of the ADAnCR0H register of channel 0 is compared with the value of the ADAnPFT register.
Page 690 Chapter 19 A/D Converter (ADC) (a) Timing example ANI0 Data Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 conversion ANI0) ANI1) ANI2) ANI3) ANI0) ANI1) ANI2) Data 1 Data 2...
Page 691 A/D Converter (ADC) Chapter 19 One-shot select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
Page 692 Chapter 19 A/D Converter (ADC) One-shot scan mode In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin to the pin specified by the ADAnS register are stored, and the set value of the ADAnCR0H register of channel 0 is compared with the value of the ADAnPFT register.
Page 693 A/D Converter (ADC) Chapter 19 (a) Timing example ANI0 Data Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 conversion ANI0) ANI1) ANI2) ANI3) Data 1 Data 2 Data 3 Data 4 ADA0CRn ANI0) (ANI1)
Page 694: Cautions
Chapter 19 A/D Converter (ADC) 19.5 Cautions When A/D Converter is not used When the A/D Converter is not used, the power consumption can be reduced by clearing the ADAnCE bit and the ADAnPS bit of the ADAnM0 register to 0. Input range of ANInm pins Input the voltage within the specified range to the ANInm pins.
Page 695 A/D Converter (ADC) Chapter 19 Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADAnS register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADAnS register is rewritten.
Page 696: How To Read A/D Converter Characteristics Table
Chapter 19 A/D Converter (ADC) 19.6 How to read A/D Converter characteristics table This section describes the terms related to the A/D Converter. For details refer to the Electrical Target Specification Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
Page 697 A/D Converter (ADC) Chapter 19 1 ..1 Ideal line Overall error 0 ..0 Analog input Figure 19-14 Overall error Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D Converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization error is unavoidable.
Page 698 Chapter 19 A/D Converter (ADC) Zero-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 0…000 to 0…001 (1/2 LSB). Ideal line Zero-scale error −1 Analog input (LSB) Figure 19-16 Zero-scale error User’s Manual U18743EE1V2UM00...
Page 699 A/D Converter (ADC) Chapter 19 Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 0…111 (full scale - 3/2 LSB). Full-scale error 2 AV REF −...
Page 700 Chapter 19 A/D Converter (ADC) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0.
Page 701: Chapter 20 Power Supply Scheme
Chapter 20 Power Supply Scheme The microcontroller has general power supply pins for its core, internal memory and peripherals. These pins are connected to internal voltage regulators. The microcontroller also has dedicated power supply pins for certain I/O modules. These pins provide the power for the I/O operations. 20.1 Overview The following table gives the naming convention of the pins: Table 20-1...
Page 702: Description
Chapter 20 Power Supply Scheme 20.2 Description Following figures give an overview of the allocation of power supply pins on the chip. Note The diagrams do not show the exact pin location. V850ES/FE3-L, V850ES/FF3-L power supply pins assignment Figure 20-1 V850ES/FE3-L, V850ES/FF3-L power supply pins assignment User’s Manual U18743EE1V2UM00...
Page 703: Voltage Regulators
Power Supply Scheme Chapter 20 V850ES/FG3-L power supply pins assignment AVREF0 A/D converter BVDD I/O buffer Flash Regulator memory BVDD REGC Main and Sub oscillators Internal circ uit EVDD EVDD I/O buffer Bidirectional level shifter Figure 20-2 V850ES/FG3-L ower supply pins assignment 20.3 Voltage regulators The on-chip voltage regulators generate the voltages for the internal circuitry, refer to Figure 20-1, Figure 20-2.
Page 704 Chapter 20 Power Supply Scheme User’s Manual U18743EE1V2UM00...
Page 705: Chapter 21 Reset
Chapter 21 Reset Several reset functions are provided in order to initialize hardware and registers. 21.1 Overview Features summary An internal system reset SYSRES can be generated by the following sources: • External reset signal RESET • Power-On-Clear (RESPOC) • Watchdog Timer 2 (RESWDT2) •...
Page 706 Chapter 21 Reset Hardware status With each reset function the hardware is initialized. When the reset status is released, program execution is started. The following table describes the status of the clocks and on-chip modules during reset and after reset release. Table 21-1 Hardware status during and after reset Item...
Page 707 Reset Chapter 21 Register status With each reset function the registers of the CPU, internal RAM, and on-chip peripheral I/Os are initialized. After a reset, make sure to set the registers to the values needed within your program. Table 21-2 Initial values of CPU and internal RAM after reset Initial value On-chip hardware...
Page 708: Reset At Power-On
Chapter 21 Reset 21.1.2 Reset at power-on The Power-On-Clear circuit (POC) permanently compares the power supply voltage V with an internal reference voltage (V ). It ensures that the microcontroller only operates as long as the power supply exceeds a well- defined limit.
Page 709 Reset Chapter 21 Figure 21-3 on page 709 outlines the start up of the CPU system after Power- On-Clear. MainOSC Stop MainOSC start possible 8 MHz internal oscillator f Stop PLL output PLLO Stop PLL enable possible CPU system clock f VBCLK CPU system f operation...
Page 710: External Reset
Chapter 21 Reset 21.1.3 External RESET Reset is performed when a low level signal is applied to the RESET pin. The reset status is released when the signal applied to the RESET pin changes from low to high. After the external RESET is released, the RESF register is cleared and the internal system reset signal SYSRES is generated.
Page 711: Reset By Watchdog Timer 2
Reset Chapter 21 21.1.4 Reset by Watchdog Timer 2 The Watchdog Timer can be configured to generate a reset if the watchdog time overflows. After watchdog reset, the RESF.WDT2RF bit is set. The system reset signal SYSRES is generated. After Watchdog Timer overflow, the reset status lasts for a specific time. Then the reset status is automatically released.
Page 712: Reset Registers
Chapter 21 Reset 21.2 Reset Registers The reset functions are controlled and operated by means of the following registers: Table 21-3 Reset function register overview Register name Shortcut Address Reset source flag register RESF FFFF F888 RESF - Reset source flag register The 8-bit RESF register contains information about which type of resets occurred since the last Power-On-Clear or external RESET.
Page 713: Chapter 22 Low-Voltage Detector
Chapter 22 Low-Voltage Detector This chapter describes the Low-Voltage Detector and the RAM data rentention function. 22.1 Functions The Low-Voltage Detector (LVI) has the following functions. • Compares the supply voltage (V ) with a reference voltage (V ) and generates –...
Page 714: Registers
Chapter 22 Low-Voltage Detector N-ch voltage Internal reset signal detection level selector − INTLVIH INTLVIL Reference voltage source (V Low voltage detection level Low voltage detection selection register (LVIS) register (LVIM) Internal bus Figure 22-1 Block diagram of Low-Voltage Detector 22.3 Registers The Low-Voltage Detector is controlled by the following registers.
Page 715 Low-Voltage Detector Chapter 22 LVIMD Selection of operation mode of low voltage detection Generate interrupt request signal • INTLVIL when supply voltage V < reference voltage V • INTLVIH when supply voltage V > reference voltage V Generate internal reset signal LVIRES when supply voltage V <...
Page 716 Chapter 22 Low-Voltage Detector LVIS - Low voltage detection level selection register The LVIS register is used to select the level of low voltage to be detected. This register can be read or written in 8-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF891H LVIS...
Page 717 Low-Voltage Detector Chapter 22 RAMS - Internal RAM data status register The RAMS register is a flag register that indicates that the supply voltage has dropped below a specific data retention voltage. If so, the contents of the RAM may have changed and has to be considered as invalid. This register can be read or written in 8-bit or 1-bit units.
Page 718 Chapter 22 Low-Voltage Detector PEMU1 - Peripheral emulation register 1 When an in-circuit emulator is used, the operation of the RAM retention flag (RAMF bit: bit 0 of RAMS register) can be pseudo-controlled and emulated by manipulating this register on the debugger. This register can be read or written in 8-bit or 1-bit units.
Page 719: Operation
Low-Voltage Detector Chapter 22 22.4 Operation Depending on the setting of the LVIMD bit, the interrupt signals (INTLVIL, INTLVIH) or an internal reset signal is generated. How to specify each operation is described below, together with timing charts. 22.4.1 Reset generation from LVI (LVIM.LVIMD = 1) Operation start 1.
Page 720: Interrupt Generation From Lvi (Lvim.lvimd = 0)
Chapter 22 Low-Voltage Detector Supply voltage LVI detection voltage (V POC detection voltage (V Time LVIM.LVION RESLVI Cleared by instruction RESF.LVIRF RESPOC SYSRES : Delay of analog circuitry Figure 22-2 Operation timing of Low-Voltage Detector (LVIMD = 1) Note During the period in which the supply voltage is the set low voltage or lower, the internal reset signal is retained (internal reset state).
Page 721: Disabling The Lvi Operation
Low-Voltage Detector Chapter 22 Supply voltage LVI detection voltage (V POC detection voltage (V Time LVIM.LVION INTLVIL INTLVIH LVIM.LVIF RESPOC SYSRES : Delay of analog circuitry Figure 22-3 Operation timing of Low-Voltage Detector (LVIM.LVIMD = 0) Note If VDD is fluctuating around the LVI detection level (VLVI), note that the judgment upon the INTLVIH or INTLVIL interrupt servicing may be incorrect.
Page 722: Ram Retention Voltage Detection Operation
Chapter 22 Low-Voltage Detector 22.4.4 RAM retention voltage detection operation The supply voltage and the data retention voltage are compared. When the supply voltage drops below the data retention voltage (including power on application), the RAMS.RAMF bit is set. For the specification of the data retention voltage, consult the Electrical Target Specification.
Page 723: Chapter 23 On-Chip Debug Unit
Chapter 23 On-Chip Debug Unit The microcontroller includes an on-chip debug unit. By connecting an N-Wire emulator, on-chip debugging can be executed. 23.1 Functional Outline 23.1.1 Debug functions Debug interface Communication with the host machine is established by using the DRST, DCK, DMS, DDI, and DDO signals via an on-chip debug emulator.
Page 724 Chapter 23 On-Chip Debug Unit Debug monitor function A memory space for debugging that is different from the user memory space is used during debugging (background monitor mode). The user program can be executed starting from any address. While execution of the user program is aborted, the user resources (such as memory and I/O) can be read and written, and the user program can be downloaded.
Page 725 On-Chip Debug Unit Chapter 23 (13) Security function This microcontroller has a N-Wire security function, that demands the user to input an ID code upon start of the debugger. For further information concerning N-Wire security, refer to “Data Protection and Security” on page 289. User’s Manual U18743EE1V2UM00...
Page 726: Controlling The N-Wire Interface
Chapter 23 On-Chip Debug Unit 23.2 Controlling the N-Wire Interface The N-Wire interface pins DRST, DDI, DDO, DCK, DMS are shared with port functions, see Table 23-1. During debugging the respective device pins are forced into the N-Wire interface mode and port functions are not available. Note that N-Wire debugging must be generally permitted by the security bit in the ID code region (*0x0000 0079[bit7] = 1) of the code flash memory.
Page 727 On-Chip Debug Unit Chapter 23 and the N-Wire debug circuit is disabled. The first CPU instructions after RESPOC can not be controlled by the debugger. The application software must set OCDM.OCDM0 = 1 in order to enable the N-Wire interface and allow debugger access to the on-chip debug unit.
Page 728: N-Wire Enabling Methods
Chapter 23 On-Chip Debug Unit 23.3 N-Wire Enabling Methods The current operation mode of the microcontroller is determined by OCDM.OCDM0 and DRST: Table 23-2 Normal operation and debug mode control DRST OCDM.OCDM0 Mode normal operation on-chip debug 23.3.1 Starting normal operation after RESET and RESPOC For “normal operation”...
Page 729: N-Wire Activation By Reset Pin
On-Chip Debug Unit Chapter 23 Figure 23-2. This will cause the program to restart. However the status of the controller might not be the same as immediately after RESPOC, since the internal RAM may have already been initialized, when the external RESET is applied.
Page 730: Connection To N-Wire Emulator
23.4.1 KEL connector KEL connector product names: • 8830E-026-170S (KEL): straight type • 8830E-026-170L (KEL): right-angle type Figure 23-4 Connection to N-Wire emulator (NEC Electronics IE-V850E1-CD-NW: N-Wire Card) User’s Manual U18743EE1V2UM00...
Page 731 On-Chip Debug Unit Chapter 23 Pin configuration Figure 23-5 shows the pin configuration of the connector for emulator connection (target system side), and Table 23-3 on page 732 shows the pin functions. Figure 23-5 Pin configuration of connector for emulator connection (target system side) Caution Evaluate the dimensions of the connector when actually mounting the...
Page 732 Chapter 23 On-Chip Debug Unit Pin functions The following table shows the pin functions of the connector for emulator connection (target system side). “I/O” indicates the direction viewed from the device. Table 23-3 Pin functions of connector for emulator connection (target system side) Pin no.
Page 733 On-Chip Debug Unit Chapter 23 Example of recommended circuit An example of the recommended circuit of the connector for emulator connection (target system side) is shown below. V850 KEL connector 8830E-026-170S Note 3 (Reserved 1) (Reserved 2) (Reserved 3) (Reserved 4) (Reserved 5) (Reserved 6) Note 1...
Page 734: Restrictions And Cautions On On-Chip Debug Function
Chapter 23 On-Chip Debug Unit 23.5 Restrictions and Cautions on On-Chip Debug Function • Do not mount a device that was used for debugging on a mass-produced product (this is because the code flash memory was rewritten during debugging and the number of rewrites of the code flash memory cannot be guaranteed).
Page 735: Chapter 24 Differences Fx3-L To Fx3
Chapter 24 Differences Fx3-L to Fx3 The following table give a short overview of the main differences between the Fx3-L series of devices and the Fx3 series of devices. Table 24-1 Feature Fx3-L Operation speed 20 MHz 32Mhz Data Flash Not available 32Kb Not available...
Page 736 Chapter 24 Differences Fx3-L to Fx3 User’s Manual U18743EE1V2UM00...
Page 737: Appendix A Special Function Registers
Appendix A Special Function Registers The following tables list all registers that are accessed via the NPB (NEC peripheral bus). The registers are called “special function registers” (SFR). Table A-1 lists all CAN special function registers. The addresses are given as offsets to the programmable peripheral base address (refer to “CAN module...
Page 738 Appendix A Special Function Registers Table A-1 CAN special function registers (2/2) Address offset Register name Shortcut 0x064 CAN0 module transmit history list register C0TGPT 0x066 CAN0 module time stamp register C0TS 0x100 to 0x4EF CAN0 Message Buffer registers, see Table 18-20 on page 556 User’s Manual U18743EE1V2UM00...
Page 739: Other Special Function Registers
Special Function Registers Appendix A A.2 Other Special Function Registers Table A-2 Other special function registers (1/9) Address Register name Shortcut 0xFFFFF004 PortDL 0xFFFFF004 PortDL low byte PDLL R/W R/W 0xFFFFF005 PortDL high byte PDLH R/W R/W 0xFFFFF008 PortCS R/W R/W 0xFFFFF00A PortCT R/W R/W...
Page 740 Appendix A Special Function Registers Table A-2 Other special function registers (2/9) Address Register name Shortcut 0xFFFFF10C Interrupt mask control register 6L IMR6L R/W R/W 0xFFFFF10D Interrupt mask control register 6H IMR6H R/W R/W 0xFFFFF10E Interrupt mask control register 7 IMR7 0xFFFFF10E Interrupt mask control register 7L...
Page 741 Special Function Registers Appendix A Table A-2 Other special function registers (3/9) Address Register name Shortcut 0xFFFFF164 Interrupt control register ADIC R/W R/W 0xFFFFF166 Interrupt control register C0ERRIC R/W R/W 0xFFFFF168 Interrupt control register C0WUPIC R/W R/W 0xFFFFF16A Interrupt control register C0RECIC R/W R/W 0xFFFFF16C...
Page 742 Appendix A Special Function Registers Table A-2 Other special function registers (4/9) Address Register name Shortcut 0xFFFFF21D ADC0 conversion result register 6H ADA0CR6H 0xFFFFF21E ADC0 conversion result register 7 ADA0CR7 0xFFFFF21F ADC0 conversion result register 7H ADA0CR7H 0xFFFFF220 ADC0 conversion result register 8 ADA0CR8 0xFFFFF221 ADC0 conversion result register 8H...
Page 743 Special Function Registers Appendix A Table A-2 Other special function registers (5/9) Address Register name Shortcut 0xFFFFF427 Port mode register3H PM3H R/W R/W 0xFFFFF428 Port mode register4 R/W R/W 0xFFFFF42A Port mode register5 R/W R/W 0xFFFFF42E Port mode register7L PM7L R/W R/W 0xFFFFF42F Port mode register7H...
Page 744 Appendix A Special Function Registers Table A-2 Other special function registers (6/9) Address Register name Shortcut 0xFFFFF5A2 TAA1 I/O control register 0 TAA1IOC0 R/W R/W 0xFFFFF5A3 TAA1 I/O control register 1 TAA1IOC1 R/W R/W 0xFFFFF5A4 TAA1 I/O control register 2 TAA1IOC2 R/W R/W 0xFFFFF5A5...
Page 745 Special Function Registers Appendix A Table A-2 Other special function registers (7/9) Address Register name Shortcut 0xFFFFF690 TMM0 timer control register0 TM0CTL0 R/W R/W 0xFFFFF694 TMM0 compare register 0 TM0CMP0 0xFFFFF6C0 Oscillation stabilization time select register OSTS 0xFFFFF6C1 PLL lockup time specification register PLLS 0xFFFFF6C2 Oscillation stabilization timer status register...
Page 746 Appendix A Special Function Registers Table A-2 Other special function registers (8/9) Address Register name Shortcut 0xFFFFFA11 UARTD1 control register 1 UD1CTL1 0xFFFFFA12 UARTD1 control register 2 UD1CTL2 0xFFFFFA13 UARTD1 option control register 0 UD1OPT0 R/W R/W 0xFFFFFA14 UARTD1 status register UD1STR R/W R/W 0xFFFFFA15...
Page 747 Special Function Registers Appendix A Table A-2 Other special function registers (9/9) Address Register name Shortcut 0xFFFFFC47 Pull-up resistor option register 3H PU3H R/W R/W 0xFFFFFC48 Pull-up resistor option register 4 R/W R/W 0xFFFFFC4A Pull-up resistor option register 5 R/W R/W 0xFFFFFC4C Pull-up resistor option register 6 0xFFFFFC52 Pull-up resistor option register 9...
Page 748 Appendix A Special Function Registers User’s Manual U18743EE1V2UM00...
Page 749: Appendix B Registers Access Times
Appendix B Registers Access Times This chapter provides formulas to calculate the access time to registers, which are accessed via the peripheral I/O areas. All accesses to the peripheral I/O areas are passed over to the NPB bus via the VSB - NPB bus bridge BBR. Read and write access times to registers via the NPB depend on the register, the system clock VBCLK and the setting of the VSWC register.
Page 750 Appendix B Registers Access Times Formula • if TAAnCTL0.TAAnCE = 0: ⋅ SUWL VSWL ----------------- - VBCLK • if TAAnCTL0.TAAnCE = 1: ⋅ ⋅ ----------------- - SUWL 2 VSWL VBCLK Access Formula • if TAAnCTL0.TAAnCE = 0: ⋅ ----------------- - SUWL VSWL VBCLK...
Page 751: Timer M
Registers Access Times Appendix B Register TAAnCNT Access Formula • if TAAnCTL0.TAAnCE = 0: ⋅ SUWL VSWL ----------------- - VBCLK • if TAAnCTL0.TAAnCE = 1: ⋅ ⋅ ----------------- - SUWL 2 VSWL VBCLK Access ⋅ Formula ----------------- - SUWL VSWL VBCLK Register all other...
Page 752: Watchdog Timer 2
Appendix B Registers Access Times B.3 Watchdog Timer 2 Register WDTM2 Access Formula • if Watchdog Timer operating: ⋅ ⋅ SUWL 4 VSWL ----------------- - VBCLK • if Watchdog Timer stopped: ⋅ ----------------- - SUWL VSWL VBCLK Access ⋅ Formula ----------------- - SUWL VSWL...
Page 753: I2C Bus
Registers Access Times Appendix B B.5 I C Bus Register IICSn Access ⋅ ⋅ Formula SUWL 3 VSWL ----------------- - VBCLK Register all other Access ⋅ Formula SUWL VSWL ----------------- - VBCLK B.6 Asynchronous Serial Interface (UARTD) Register Access ⋅ Formula ----------------- - SUWL...
Page 754: Can Controller
Appendix B Registers Access Times B.8 CAN Controller Register CnMDATA[7:0]m Access VBCLK ⎧ ⎫ ⋅ ----------------- - ⎪ ⎪ ⋅ ⋅ ⎨ ⎬ Formula SUWL VSWL ----------------------------------- - VSWL ----------------- - VSWL ⎪ ⎪ VBCLK ⎩ ⎭ Access 8-bit Write VBCLK ⎧...
Page 755: Revision History
Revision History Version Date Document number Description August 2007 U18743EE1V0UM00 Initial release April 2008 U18743EE1V1UM00 Update June 2008 U18743EE1V2UM00 Update The following revision list shows all functional changes compared to the manual version U18743EE1V1UM00 (published in April 2008). Chapter Page Description Corrected number of writable bytes in flash memory.
Page 756 User’s Manual U18743EE1V2UM00...
Page 757: Index
Index (ADAnCRSS) 677 AVSS A/D conversion diagnostic registers (ADAnCRSSH) 677 A/D Converter 663 Basic operation 680 Baud rate generator Cautions 694 UARTD 419 Configuration 665 BCU (Bus Control Unit) 295 Control registers 667 BCU registers 301 How to read A/D Converter characteristics Boundary operation conditions 299 table 696 BPC 301...
Page 758 Index CANn global automatic block transmission delay General registers 168 register (CnGMABTD) 567 Operation 191 CANn global clock selection register PLL related registers 178 (CnGMCS) 564 Registers 166 CANn global control register (CnGMCTRL) 562 Start conditions 165 CANn message configuration register m Clock Monitor 163 (CnMCONFm) 592 Control registers 184...
Page 759 Index CPU operation clock status register (CCLS) 168 Flash memory 259 CSIB Self-programming 277 Configuration 428 Flash programmer Control registers 430 Communication mode 267 Operation 436 Pin connection 269 Operation flow 449 Flash programming Output pins 448 Mode 146 CSIB (Clocked Serial Interface) 427 FLIC 237 CSIB transmit data register (CBnTX) 429 fPLLI 161...
Page 760 Index IIC shift registers (IICn) 479 (LVIS) 716 IIC status registers (IICSn) 467 Low voltage detection register (LVIM) 714 IIC0IC 237 Low Voltage Detector 713 IICCLn 472 Configuration 713 IICCn 463 Operation 719 IICFn 470 Registers 714 IICn 479 LVIHIC 237 IICSn 467 LVILIC 237 IICXn 473...
Page 761 Index Internal oscillator 160 POC (Power-On Clear) 708 Main oscillator 160 Port function control expansion register (PFCEn) 41 Sub oscillator 160 Port function control register (PFCn) 40 OSTC 170 Port function register (PFn) 46 OSTS 171 Port groups 32 Configuration 51 Package pins assignment 132 Configuration registers 36 PC 140...
Page 762 Index Reset 705 TAA I/O control register 2 (TAAnIOC2) 321 At power-on 708 TAA I/O control register 4 (TAAnIOC4) 323 By clock monitor 711 TAA option register 0 (TAAnOPT0) 324 By Watchdog Timer 711 TAA option register 1 (TAAnOPT1) 325 External reset 710 TAA timer control register 1 (TAAnCTL1) 316 Hardware status after reset 706...
Page 763 Index UARTDn control register 2 (UDnCTL2) 421 UARTDn option control register 0 Zero register 138 (UDnOPT0) 397 UARTDn option control register 1 (UDnOPT1) 399 UARTDn receive data register (UDnRX) 402 UARTDn receive shift register 393 UARTDn status register (UDnSTR) 400 UARTDn transmit data register (UDnTX) 402 UARTDn transmit shift register 394 UD0RIC 237...
Page 764 User’s Manual U18743EE1V2UM00...

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NEC V850ES/F 3-L Series User Manual

Chapter 1 Introduction

General

Features Summary

Description

Ordering Information

Chapter 2 Pin Functions

Overview

Port Group Configuration Registers

Port Buffers Diagrams

Port Type Diagrams

Port Group Configuration

Noise Elimination

Pin Functions in Reset and Power Save Modes

Recommended Connection of Unused Pins

Package Pins Assignment

Chapter 3 CPU System Functions

Overview

CPU Register Set

Operation Modes

Address Space

Memory

Write Protected Registers

Chapter 4 Clock Generator

Overview

Clock Generator Registers

Option Bytes

Clock Generator Operation

Chapter 5 Interrupt Controller (INTC)

Features

Non-Maskable Interrupts

Maskable Interrupts

External Interrupts Edge Detection Configuration

Software Exception

Exception Trap

Multiple Interrupt Processing Control

Interrupt Response Time

Periods in Which Interrupts Are Not Acknowledged

Chapter 6 Key Interrupt Function

Function

Control Register

Cautions

Chapter 7 Flash Memory

Code Flash Memory Overview

Flash Programming with Flash Programmer

Code Flash Self-Programming

Variable Reset Vector

Flash Mask Options

Chapter 8 Data Protection and Security

Overview

N-Wire Debug Interface Protection

Flash Programmer and Self-Programming Protection

Chapter 9 Bus Control Unit (BCU)

Description

Registers

Chapter 10 16-Bit Timer/Event Counter AA

Features

Function Outline

Configuration

Input Selection Registers

Control Registers

Operation

Chapter 11 16-Bit Interval Timer M

Features

Configuration

Timer M Registers

Operation

Chapter 12 Timer AA Synchroneous Operation

Chapter 13 Watch Timer Functions

Functions

Configuration

Control Registers

Operation

Chapter 14 Watchdog Timer 2

Functions

Configuration

Control Registers

Watchdog Timer Operation

Watchdog Timer Operation in Power Save Mode

Chapter 15 Asynchronous Serial Interface (UARTD)