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Chapter 15
15.5.11 Receive data noise filter
Base clock (f
)
UCLK
RXDAn
Figure 15-9
Base clock
RXDDn (input)
Internal signal A
Internal signal B
Internal signal C
Figure 15-10
418
This filter samples the RXDDn pin using the base clock of the prescaler output.
When the same sampling value is read twice, the match detector output
changes and the RXDDn signal is sampled as the input data. Therefore, data
not exceeding 2 clock width is judged to be noise and is not delivered to the
internal circuit (see Figure 15-10). See "Base clock" on page 419 regarding the
base clock.
Moreover, since the circuit is as shown in Figure 15-9, the processing that
goes on within the receive operation is delayed by 3 clocks in relation to the
external signal status.
Internal signal A
In
Q
Noise filter circuit
Match
Timing of RXDDn signal judged as noise
User's Manual U18743EE1V2UM00
Asynchronous Serial Interface (UARTD)
Internal signal B
In
Q
Match
detector
Mismatch
(judged as noise)
In
Q
Internal signal C
LD_EN
Match
Mismatch
(judged as noise)
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