Periods In Which Interrupts Are Not Acknowledged - NEC V850ES/F 3-L Series User Manual

Interrupt Controller (INTC)
Interrupt response time (internal system clocks)
Internal interrupt
Minimum
6 (in case of latency = 2)
Maximum
7 (in case of latency = 3)

5.9 Periods in which interrupts are not acknowledged

External interrupt
4 4 + analog delay time
6 + analog delay time
(in case of latency = 2)
7 + analog delay time
(in case of latency = 3)
An interrupt is acknowledged while an instruction is being executed. However,
no interrupt will be acknowledged between an interrupt non-sample instruction
and the next instruction.
The interrupt request non-sampling instructions are as follows:
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (for PSW)
• The store instruction for the interrupt control register (PlCn), in-service
priority register (ISPR), and command register (PRCMD).• The store
instruction for the following registers and SET1, NOT1, CLR1 instruction.
• Interrupt registers:
Interrupt control register (xxICn), interrupt mask registers 0 to 7 (IMR0 to
IMR7)
• In-service priority register (ISPR)
• Command register (PRCMD)
• Power save control register (PSC)
• On-chip debug mode register (OCDM)
Peripheral emulation register 1 (PEMU1)
User's Manual U18743EE1V2UM00
Condition
The following cases are exceptions:
• In IDLE/software STOP mode
• External bit access
• Two or more interrupt request non-
sample instructions are executed
• Access to interrupt control register
Chapter 5
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