Table of Contents
Advertisement
Clock Generator
Clock for WDT2
(4)
(5)
4.1.2 Clock Monitor
This is the clock for the Watchdog Timer. The clock for WDT2 is available (and
hence the Watchdog Timer running) as long as the chosen clock source (240
KHz internal oscillator or MainOSC) is active.
Note that the WDT2 operation is defined in option byte 007A
Stand-by control
In the block diagram, you find also boxes labelled "IDLE Control" or "HALT
control". These boxes symbolize the switches that are used to disable circuits
when the microcontroller enters one of the various power save modes.
For an introduction, see "Power save modes overview" on page 164.
Summary of clock signals
f
:
MainOSC clock is input clock to PLL
X
f
:
SubOSC clock
XT
f
:
240 KHz internal oscillator clock
RL
f
:
8 MHz internal oscillator clock
RH
f
:
PLL input clock. Can be f
PLLI
f
:
PLL output clock
PLLO
f
:
PLL output clock
PLL
f
:
Main system clock
XX
f
:
CPU system clock
VBCLK
f
:
CPU core clock (same clock as f
CPU
f
:
Peripheral clock 1 (output of Prescaler1, stops in IDLE1 mode)
XP1
f
:
Peripheral clock 2 (same frequency as f
XP2
mode)
f
:
MainOSC clock for CANn interfaces (same frequency as f
XC
IDLE1 and IDLE2 mode)
f
:
Sub clock
SC
The Clock Monitor supervises the operation of the MainOSC. In case of
malfunction, the Clock Monitor can generate a system reset.
The monitor requires that the built-in 240 KHz internal oscillator is active. For
details see "Operation of the Clock Monitor" on page 217.
User's Manual U18743EE1V2UM00
or a fraction of f
X
X
, but stops in HALT mode)
VBCLK
, but continues in IDLE1
XP1
Chapter 4
.
H
, stops in
X
163
Advertisement
Table of Contents
