NEC V850ES/F 3-L Series User Manual page 231

Interrupt Controller (INTC)
INTC accepted
CPU processing
Figure 5-5
Note
INT input
xxIF = 1
Yes
xxMK = 0
Yes
Priority higher than
that of interrupt currently
processed?
Yes
Priority higher
than that of other interrupt
request?
Yes
Highest default
priority of interrupt requests
with the same priority?
Yes
Maskable interrupt request
PSW.NP
0
PSW.ID
0
EIPC restored PC
EIPSW PSW
ECR.EICC exception code
PSW.EP 0
PSW.ID 1
PC handler address
Interrupt processing
Maskable interrupt processing
For the ISPR register, see "ISPR - In-service priority register" on page 242.
An INT input masked by the Interrupt Controllers and an INT input that occurs
while another interrupt is being processed (when PSW.NP = 1 or PSW.ID = 1)
are held pending internally by the Interrupt Controller. In such case, if the
interrupts are unmasked, or when PSW.NP = 0 and PSW.ID = 0 as set by the
RETI and LDSR instructions, input of the pending INT starts the new maskable
interrupt processing.
User's Manual U18743EE1V2UM00
No
No
Is the interrupt
mask released?
No
No
No
Interrupt request pending
1
1
Interrupt request pending
Chapter 5
231