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Chapter 4
Table 4-27
Power-On-Clear circuit
Low-Voltage Detector
Voltage Regulator
Internal data
a)
Only when setting the ISELxx bit =1 (f
b)
To achieve low power consumption, stop the A/D Converter before shifting to the IDLE1 mode.
Leaving IDLE1
mode
Note
200
Controller status in IDLE1 mode (2/2)
Without Subclock
Operable
Operable
Operation continues
The CPU registers, states, data and all other internal data such as the contents of
the internal RAM are retained as they were before IDLE1 mode was set
), the count operation by f
XP2
The IDLE1 mode is released by a non-maskable interrupt request signal (NMI
pin input or INTWDT2 signal), unmasked external interrupt request signal,
unmasked internal interrupt request signal of a peripheral function that can
operate in the IDLE1 mode, or reset signal.
Interrupt request signals that are disabled by the NMI1M, NMI0M, and INTM
bits of the PSC register are invalid and do not release the IDLE1 mode.
When digital noise elimination is enabled for INTP3, the power save mode
cannot be released using INTP3 pin. For details, refer to "Pin Functions" on
page 31.
When the IDLE1 mode has been released, the normal operation mode is
restored.
User's Manual U18743EE1V2UM00
Working condition
With Subclock
is also possible.
XT
Clock Generator
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