Multiple Interrupt Processing Control - NEC V850ES/F 3-L Series User Manual

Chapter 5
Figure 5-15

5.7 Multiple Interrupt Processing Control

252
Figure 5-15 illustrates the restore processing from a debug trap.
Restore processing from debug trap
Multiple interrupt processing control is a process by which an interrupt request
that is currently being processed can be interrupted during processing if there
is an interrupt request with a higher priority level, and the higher priority
interrupt request is received and processed first.
If there is an interrupt request with a lower priority level than the interrupt
request currently being processed, that interrupt request is held pending.
Maskable interrupt multiple processing control is executed when an interrupt
has an enable status (ID = 0). Thus, if multiple interrupts are executed, it is
necessary to have an interrupt enable status (ID = 0) even for an interrupt
processing routine.
If a maskable interrupt enable or a software exception is generated in a
maskable interrupt or software exception service program, it is necessary to
save EIPC and EIPSW.
This is accomplished by the following procedure.
User's Manual U18743EE1V2UM00
DBRET instruction
PC DBPC
PSW DBPSW
Jump to address of restored PC
Interrupt Controller (INTC)