Write Protected Registers - NEC V850ES/F 3-L Series User Manual

CPU System Functions

3.6 Write Protected Registers

Table 3-13
Write protected register
Processor clock control register
Main system clock mode register
Clock Monitor mode register
Power save control register
Reset source flag register
Internal RAM data status register
Low-voltage detection register
On-chip debug mode register
Example
Note
Write protected registers are protected from inadvertent write access due to
erroneous program execution, etc. Write access to a write protected register is
only given immediately after writing to a corresponding write enable register.
For a write access to the write protected registers you have to use the following
instructions:
1. Store instruction (ST/SST instruction)
2. Bit operation instruction (SET1/CLR1/NOT1 instruction)
Incorrect store operations can be checked by a flag of the system status
register (SYS).
When reading write protected registers, no special sequence is required.
The following table gives an overview of the write protected registers and their
corresponding write enable registers.
Overview of write protected registers
Shortcut
PCC
MCM
CLM
PSC
RESF
RAMS
LVIM
OCDM
Enable Clock Monitor
The following example shows how to write to the write protected register CLM.
The example enables the Clock Monitor.
do {
_PRERR = 0;
DI();
PRCMD = 0x5A;
CLM = 0x01;
EI();
} while (_PRERR != 0)
1. Make sure that the compiler generates two consecutive assembler "store"
instructions to PRCMD and CLM from the associated C statements.
2. Special care must be taken when writing to registers PSC and PRCMD.
Please refer to "Clock Generator" on page 179 for details.
3. Any value can be written to the PRMCD register.
User's Manual U18743EE1V2UM00
Corresponding write
Shortcut For details see
enable register
Command register
"Clock Generator" on
page 179
PRCMD
"Reset" on page 705
"Low-Voltage Detector"
on page 713
"On-Chip Debug Unit" on
page 723
Chapter 3
155