Table of Contents
Advertisement
Chapter 4
(3)
HALT mode
X1 = ON, PLL = OFF
Figure 4-5
Note
194
Status transition from main clock-through operation (with PLL off)
X1 main clock-through mode
IDLE1 mode
X1 = ON, PLL = OFF
Stand-by transition from x1 main clock-through operation (PLL = OFF)
1.
After the time set by the OSTS register has elapsed, the CPU returns to
the through mode.
2.
After the time set by the OSTS register has elapsed, the CPU returns to
the through mode. If the Watchdog Timer overflows (reset) while the
oscillation stabilization time is counted, the CPU starts its clock operation
with the internal oscillator.
User's Manual U18743EE1V2UM00
(PLL = OFF)
Note 1
IDLE2 mode
X1 = ON, PLL = OFF
Clock Generator
Note 2
Software STOP mode
X1 = OFF, PLL = OFF
Advertisement
Table of Contents
