External Reset - NEC V850ES/F 3-L Series User Manual

Chapter 21

21.1.3 External RESET

MainOSC
f
x
8 MHz internal
oscillator f
RH
PLL output
f
PLLO
CPU system
clock f
VBCLK
RESET
analog delay
(noise removal)
Internal
reset
Figure 21-4
710
Reset is performed when a low level signal is applied to the RESET pin.
The reset status is released when the signal applied to the RESET pin
changes from low to high.
After the external RESET is released, the RESF register is cleared and the
internal system reset signal SYSRES is generated.
The RESET pin incorporates a noise eliminator, which is applied to the reset
signal RESET. To prevent erroneous external reset due to noise, it uses an
analog filter. Even if no clock is active in the controller the external RESET can
keep the controller in reset state.
The following figure shows the timing when an external RESET is performed. It
explains the effect of the noise eliminator. The noise eliminator uses the analog
delay to prevent the generation of an external reset due to noise.
The analog delay is caused by the analog input filter. The filter regards pulses
up to a certain width as noise and suppresses them. For the minimum RESET
pulse width refer to the Electrical Target Specification.
CPU system f operation
PLLO
analog delay
(reset detection)
Timing for external RESET
User's Manual U18743EE1V2UM00
Stop
Stop
Stop
analog delay analog delay
(noise removal) (reset release)
f
RH
MainOSC start possible
PLL enable possible
CPU system f operation
RH
setup time
Reset