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Asynchronous Serial Interface (UARTD)
UDnSRF
INTUDnR
interrupt
UD0SRF
INTUDnR
interrupt
Note
bits is suppressed and UART communication error detection processing is not
performed. Moreover, data transfer of the UARTDn reception shift register and
UDnRX register is not performed and FFH, the initial value, is held. If the SBF
width is 10 or fewer bits, reception is terminated as error processing without
outputting an interrupt, and the SBF reception mode is returned to. The
UDnSRF bit is not cleared at this time.
The SBF mode can be selected between a single SBF receive mode and an
any time SBF receive mode in the UDnOPT1 register (UDnOPT1.UDnSRS).
The status of a successful reception of the SBF is shown y the
UDnOPT1.UDnSRS bit in the UDnOPT1 register.
(a) Normal SBF reception (detection of stop bit in more than 10.5 bits)
1
2
3
4
(b) SBF reception error (detection of stop bit in 10.5 or fewer bits)
1
2
3
The UDnSRF bit is reset by setting the UDnSRT bit to "1", and cleared by
normal SBF reception.
User's Manual U18743EE1V2UM00
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11.5
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10.5
Chapter 15
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