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Asynchronous Serial Interface (UARTD)
(5)
After reset: 00H
7
UDnOPT1
0
R/W
R/W
Note
Note
UDnOPT1 - UARTDn option control register 1
The UDnOPT1 register is an 8-bit register that controls the serial transfer
operation of the UARTDn register.
This register can be read or written in 8-bit units.
Reset input sets this register to 00H.
Address:
6
5
0
0
R/W
R/W
UDnSRS
A new SBF can't be detected while the communication is in
0
progress.When the low level is detected at the stop bit position, it is
recognized as framing error.
A new SBF can be detected while the communication is in
progress.When the low level is detected at the stop bit position a
1
waiting state is generated until high level is detected. When the width
of the low level is 11 bits or more, it is recognized as new SBF.
1.
This bit should only be set when the LIN communication is used. Otherwise
set this bit to 0.
2.
When this bit is set to 1, it is necessary to set UD0DCS to 1.
UDnDCS
0
Data consistency is not checked
1
Data consistency is checked
When data is transmitted using the LIN protocoll, this bit selects the handling of the
consistency checking of data. When UDNDCS = 1 the transmitted data and
received data are compared and the mismatch is detected. In that case a status
interrupt request signal (UDTIS) is generated.
1.
This bit should only be set when the LIN communication is used. Otherwise
set this bit to 0.
2.
When this bit is used, the data bit length doesn't prohibits the eight bit
fixation and the addition of the parity bit.
User's Manual U18743EE1V2UM00
UD0OPT1: FFFFFA05, UD1OPT1: FFFFFA15
UD2OPT1: FFFFFA25, UD3OPT1: FFFFFA35
UD4OPT1: FFFFFA45, UD5OPT1: FFFFFA55
UD6OPT1: FFFFFA65, UD7OPT1: FFFFFA75
4
3
0
0
R/W
R/W
SBF reception mode selection bit
Data consistency check selection bit
Chapter 15
2
1
0
UDnSRS
UDnDCS
R/W
R/W
0
R/W
399
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