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Chapter 17
SPTn
0
Stop condition is not generated.
Stop condition is generated (termination of master device's transfer).
After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until it goes to
1
high level. Next, after the rated amount of time has elapsed, the SDA0n line is changed from low
level to high level and a stop condition is generated.
Cautions concerning set timing
For master reception:
For master transmission: A stop condition cannot be generated normally during the ACK period. Set (1) during
• SPTn cannot be set at the same time as the STTn bit.
• The SPTn bit can be set only when in master mode
• When the WTIMn bit has been set to 0 and the SPTn bit is set during the wait period that follows output of
eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock.
When the ninth clock must be output to apply the ACK on the bus by the receiving device, proceed as follows:
- Change IICCn.WTIMn from 0 to 1 in order to receive an additional interrupt after the ninth clock.
- Cancel the wait state by IICCn.WRELn = 1 or by writing to the IICn register.
- Upon the interrupt after the ninth clock require to set the stop condition by IICCn.STPn = 1.
By this the wait status will be cancelled and the stop condition will be generated on the bus.
• When the SPT0 bit is set to 1, setting the SPT0 bit to 1 again is disabled until the bit is cleared to 0.
Condition for clearing (SPTn = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• When the LRELn = 1 (communication save)
• When the IICEn = 0 (operation stop)
• After reset
Note
Caution
466
Cannot be set during transfer.
Can be set only when the ACKEn bit has been set to 0 and during the wait period after
the slave has been notified of final reception.
the wait period.
Note 2
1.
Set the SPTn bit only in master mode. However, when the IICRSVn bit is 0,
the SPTn bit must be set and a stop condition generated before the first
stop condition is detected following the switch to the operation enabled
status. For details, see "Cautions" on page 511.
2.
Clearing the IICEn bit to 0 invalidates the signals of this flag.
3.
The SPTn bit is 0 if it is read immediately after data setting.
When the TRCn = 1, the WRELn bit is set during the ninth clock and wait is
cancelled, after which the TRCn bit is cleared and the SDA0n line is set to high
impedance.
User's Manual U18743EE1V2UM00
Stop condition trigger
Note 1
.
Condition for setting (SPTn = 1)
• Set by instruction
2
I
C Bus (IIC)
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