Pll Control Registers - NEC V850ES/F 3-L Series User Manual

Chapter 4

4.2.2 PLL control registers

(1)
Access
Address
Initial Value
Table 4-11
Bit position Bit name
0 LOCK
Set conditions
Clear conditions
Note
178
The Clock Generator's PLL registers control and reflect the operation of the
PLL.
LOCKR - PLL lock status register
Phase lock occurs at a given frequency following power application or
immediately after the STOP mode is released, and the time required for
stabilization is the lockup time (frequency stabilization time). This time until
stabilization is called the lockup status, and the stabilized state is called the
locked status.
The lock register LOCKR includes a LOCK bit that reflects the PLL frequency
stabilization status.
This register is read-only, in 8-bit or 1-bit units.
FFFF F824 .
H
01 . The register is initialized by any reset.
H
7 6 5
0 0 0
R R R
LOCKR register contents
PLL lock status check:
0: Locked status.
1: Unlocked status
The LOCK register does not reflect the lock status of the PLL in real time. The
set/reset conditions are as follows:
• Upon system reset. This register is set to 01
after the reset has been released and the oscillation stabilization time has
elapsed.
• In STOP and IDLE2 mode.
• Upon setting the PLL to stop (clearing bit PLLCTL.PLLON).
• Upon stopping the main system clock and using the CPU with subclock
(setting bits PCC.CK3 and PCC.MCK to 1).
• After reset release and overflow of oscillation stabilization time counter
(OSTS register default time).
• When bit PLLCTL.PLLON is changed from 0 to 1 after PLL lockup timer
overflow (time set by PLLS register).
• After STOP mode release and oscillation stabilization time counter overflow
(time set by OSTS register), when the STOP mode was set while the PLL
was in PLL mode.
• After IDLE2 mode release and oscillation stabilization timer overflow (time
set by OSTS register), when the IDLE2 mode was set while the PLL was in
PLL mode.
The PLL can enter the locked status only, if the MainOSC is enabled, i.e.
PCC.MCLK = 0.
User's Manual U18743EE1V2UM00
4 3 2
0 0 0
R R R
Function
H
Clock Generator
1 0
0 LOCK
R R
by reset and cleared to 00
H