Wait Signal (Wait) - NEC V850ES/F 3-L Series User Manual

Chapter 17

17.6.6 Wait signal (WAIT)

(1)
Master
IICn
SCL0n
Slave
IICn
SCL0n
ACKEn
Transfer lines
SCL0n
SDA0n
Figure 17-11
486
The wait signal (WAIT) is used to notify the communication partner that a
device (master or slave) is preparing to transmit or receive data (i.e., is in a
wait state).
Setting the SCL0n pin to low level notifies the communication partner of the
wait status. When the wait status has been cancelled for both the master and
slave devices, the next data transfer can begin.
When master device has a nine-clock wait and slave device has an eight-
clock wait (master: transmission, slave: reception, and IICCn.ACKEn
bit = 1)
Master returns to high
impedance but slave
is in wait state (low level).
6 7 8
Wait after output
of eighth clock.
H
6 7 8
D2 D1 D0
Wait signal (1/2)
User's Manual U18743EE1V2UM00
Wait after output
of ninth clock.
9
FFH is written to IICn register or
IICCn.WRELn bit is set to 1.
Wait signal
Wait signal
from master
from slave
9
ACK
2
I C Bus (IIC)
IICn data write (cancel wait)
1 2 3
1 2 3
D7 D6 D5