NEC V850ES/F 3-L Series User Manual page 709

Reset
8 MHz internal
oscillator f
PLL output
CPU system
clock f
Figure 21-3
Figure 21-3 on page 709 outlines the start up of the CPU system after Power-
On-Clear.
VDD
MainOSC
f
x
RH
Stop
f
PLLO
VBCLK
RESET
Internal
reset
CPU system start up after Power-On-Clear
User's Manual U18743EE1V2UM00
Stop
Stop
analog delay
(reset release)
f setup time
RH
Chapter 21
MainOSC start possible
PLL enable possible
CPU system f operation
RH
709