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Chapter 10
(7)
Address: TAA0OPT0 FFFFF595H, TAA1OPT0 FFFFF5A5H,
Symbol
TAAnOPT0
Caution
324
TAAnOPT0 - TAA option register 0
The TAAnOPT0 register is an 8-bit register used to set the capture/compare
operation and detect overflow.
This register can be read and written in 8-bit or 1-bit units.
RESET input clears this register to 00H.
TAA2OPT0 FFFFF5B5H, TAA3OPT0 FFFFF5C5H,
TAA4OPT0 FFFFF5D5H, TAA5OPT0 FFFFF5E5H,
TAA6OPT0 FFFFF5F5H, TAA7OPT0 FFFFF605H
7
6
5
TAAn
0
0
CCS1
TAAnCCS1
0
Compare register selection
1
Capture register selection
The TAAnCCS1 bit setting is valid only in the free-running mode.
TAAnCCS0
0
Compare register selection
1
Capture register selection
The TAAnCCS0 bit setting is valid only in the free-running mode.
TAAnOVF
Set (1)
Overflow occurrence
Reset (0)
TAAnOVF bit write or TAAnCE = 0
• The TAAnOVF bit is set when the 16-bit counter value overflows from FFFFH to
0000H in the free-running mode and the pulse width measurement mode.
• An interrupt request signal (INTTAAnOV) is generated as soon as TAAnOVF bit is
set (1).
The INTTAAnOV signal is not generated in any mode other than free-running
mode and the pulse width measurement mode.
• The TAAnOVF bit is not cleared even when the TAAnOVF bit and the TAAnOPT0
register are read when TAAnOVF = 1.
• The TAAnOVF bit can be both read and written, but 1 cannot be written to the
TAAnOVF bit from the CPU. Writing 1 has no influence on timer AA operation.
Rewrite TAAnCCS1 and TAAnCCS0 bits when TAAnCE = 0 (the same value
can be written when TAAnCE = 1.). If rewriting was mistakenly performed,
clear TAAnCE to 0 and then set the bits again.
User's Manual U18743EE1V2UM00
4
3
2
TAAn
0
0
CCS0
TAAnCCR1 register capture/compare selection
TAAnCCR0 register capture/compare selection
Timer AA overflow detection
16-Bit Timer/Event Counter AA
1
<0>
TAAn
0
OVF
After
R/W
reset
R/W 00H
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