NEC V850ES/F 3-L Series User Manual page 253

Interrupt Controller (INTC)
(1)
...
...
•EIPC saved to memory or register
•EIPSW saved to memory or register
•EI instruction (interrupt acknowledgment enabled)
...
...
...
•DI instruction (interrupt acknowledgment disabled)
•Saved value restored to EIPSW
•Saved value restored to EIPC
•RETI instruction
(2)
...
...
•EIPC saved to memory or register
•EIPSW saved to memory or register
...
•TRAP instruction
...
•Saved value restored to EIPSW
•Saved value restored to EIPC
•RETI instruction
Acknowledgment of maskable interrupts in service program
Service program of maskable interrupt or exception
Generation of exception in service program
Service program of maskable interrupt or exception
¨ Exception such as TRAP instruction acknowledged.
The priority order for multiple interrupt processing control has 8 levels, from 0
to 7 for each maskable interrupt request (0 is the highest priority), but it can be
set as desired via software. Setting of the priority order level is done using the
PPRn0 to PPRn2 bits of the interrupt control request register (PlCn), which is
provided for each maskable interrupt request. After system reset, an interrupt
request is masked by the PMKn bit and the priority order is set to level 7 by the
PPRn0 to PPRn2 bits.
The priority order of maskable interrupts is as follows.
(High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 >
Level 5 > Level 6 > Level 7
User's Manual U18743EE1V2UM00
¨ Maskable interrupt acknowledgment
(Low)
Chapter 5
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