Clock Generator Operation; Overview Of Clock Operation Control Settings - NEC V850ES/F 3-L Series User Manual

Clock Generator

4.4 Clock Generator Operation

4.4.1 Overview of clock operation control settings

Table 4-23
CCLS.CCLSF PCC.CLS
0
(Main
system
clock
operation
mode)
0
1
(Subclock
operation
mode)
1
a)
x = don't care
This chapter describes the specific features of the Clock Generator. For details
see:
• "Overview of clock operation control settings" on page 191
• "Operation state transitions" on page 192
• "Power save modes description" on page 196
• "Available clocks in power save modes" on page 211
• "Controlling the PLL" on page 215
• "Watch Dog Timer Clock" on page 215
• "CLKOUT function" on page 215
• "Operation of Prescaler3" on page 216
• "Operation of the Clock Monitor" on page 217
The following table gives an overview of the settings that specify the CPU
system clock f . It identifies the register bits that must be set or cleared to
VBCLK
generate specific f
VBCLK
CPU system clock settings
PLLCTL.SELPLL MCM.MCM0
0
(8 MHz internal
(Clock-through
oscillator mode)
mode)
1 (PLL mode)
(MainOSC
x
-
Other than above
User's Manual U18743EE1V2UM00
.
Option byte 007B:
SUBCLK bit
0
a
x
1
0
(SubOSC mode)
mode)
1
(240 KHz internal
oscillator mode 2)
Chapter 4
Operation Clock
8 MHz internal oscillator
clock operation
MainOSC clock operation
PLL operation
SubOSC clock operation
240 KHz internal oscillator
clock operation (Sub)
240 KHz internal oscillator
clock operation (Security)
Setting prohibited
191