Priorities Of Maskable Interrupts - NEC V850ES/F 3-L Series User Manual

Interrupt Controller (INTC) Chapter 5

5.3.3 Priorities of maskable interrupts

This microcontroller provides multiple interrupt servicing in which an interrupt
is acknowledged while another interrupt is being serviced. Multiple interrupts
can be controlled by priority levels.
There are two types of priority level control: control based on the default
priority levels, and control based on the programmable priority levels that are
specified by the interrupt priority level specification bit (xxPRn) of the interrupt
control register (xxICn). When two or more interrupts having the same priority
level specified by the xxPRn bit are generated at the same time, interrupts are
serviced in order depending on the priority level allocated to each interrupt
request type (default priority level) beforehand. For more information, refer to
the interrupt/exception source list table. The programmable priority control
customizes interrupt requests into eight levels by setting the priority level
specification flag.
Note that when an interrupt request is acknowledged, the ID flag of PSW is
automatically set to 1. Therefore, when multiple interrupts are to be used, clear
the ID flag to 0 beforehand (for example, by placing the EI instruction in the
interrupt service program) to set the interrupt enable mode.
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