Software Exception; Operation - NEC V850ES/F 3-L Series User Manual

Interrupt Controller (INTC)

5.5 Software Exception

5.5.1 Operation

Figure 5-10
Note
A software exception is generated when the CPU executes the TRAP
instruction, and can be always acknowledged.
If a software exception occurs, the CPU performs the following processing, and
transfers control to the handler routine:
1. Saves the restored PC to EIPC.
2. Saves the current PSW to EIPSW.
3. Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt
source).
4. Sets the EP and ID bits of the PSW.
5. Sets the handler address (00000040H or 00000050H) corresponding to
the software exception to the PC, and transfers control.
Figure 5-10 illustrates the processing of a software exception.
CPU processing
Software exception processing
TRAP Instruction Format: TRAP vector (the vector is a value from 0 to 1FH.)
The handler address is determined by the TRAP instruction's operand (vector).
If the vector is 0 to 0FH, it becomes 00000040H, and if the vector is 10H to
1FH, it becomes 00000050H.
User's Manual U18743EE1V2UM00
Note
TRAP instruction
EIPC restored PC
EIPSW PSW
ECR.EICC exception code
PSW.EP 1
PSW.ID 1
PC handler address
Exception processing
Chapter 5
247